firtool-1.145.0

What's Changed

• [ImportVerilog] Refactor HierarchicalNames to use ASTVisitor by @TaoBi22 in #10097
• Silence a warning by @darthscsi in #10099
• [NFC][ImportVerilog] Clean up unnecessary hierarchical expr visitor by @TaoBi22 in #10098
• [ImportVerilog] Add capture analysis pre-pass for functions by @fabianschuiki in #10094
• [Synth] [FunctionalReduction] Add conflict limit option, and add to circt-synth by @uenoku in #10073
• [ExportVerilog] Add ModportType support for non-extern hw.module ports by @dmlockhart in #10030
• [ImportVerilog] Use capture analysis for function declarations by @fabianschuiki in #10101
• [ImportVerilog] Support case inside statements by @sunhailong2001 in #10090
• [SMTToZ3LLVM] Strip dbg.variable and dbg.scope ops (for now) by @TaoBi22 in #10102
• [Sim][SimToSv] DPI-C Semantic preserving sim.func.dpi and sim.func.dpi.call by @pscabot in #9977
• [circt-bmc] Preserve signal names before lowering by @ankit-cybertron in #10075
• [ImportVerilog] Add basic (and/or/xor) primitive support by @TaoBi22 in #10108
• [Arc][Conversion] Lower sim.clocked_terminate to exit in LowerArcToLLVM by @nanjo712 in #10089
• [Arc] Handle sv.xmr.ref ops and hw.hierpath ops by @nanjo712 in #10096
• [ImportVerilog] Post-merge review fixes for #10108 by @TaoBi22 in #10110
• [ArcRuntime] Error on invalid trace buffer size by @fzi-hielscher in #10113
• [CMake][ArcRuntime] Tweak build of libfst by @fzi-hielscher in #10112
• [FIRRTL] InferDomains: Add debug logging by @rwy7 in #10107
• [ImportVerilog] Two-phase function conversion: declare then define by @fabianschuiki in #10111
• [SATSolver] Fix a namespace issue, NFC by @uenoku in #10117
• [HW] Add IMDCE module rewrites by @stomfaig in #10007
• [Synth][CutRewriter] Add signature filtering by @uenoku in #10120
• Revert "Revert "[CI] Cancel in-progress PR builds on new push"" by @uenoku in #10122
• [FIRRTL] Fix mask repeat order in FlattenMemory by @Waryc in #10106
• [FIRRTL] LowerDomains Domain-type Associated Wire by @seldridge in #10123
• [FIRRTL] InferDomains: Fix wire updating by @rwy7 in #10115
• [ci] Switch buildAndTest to use UBTI by @seldridge in #10135
• [FIRRTL] InferDomains: put code under a class by @rwy7 in #10145
• [ci] Only save sccache on push to main by @uenoku in #10149
• [ci] Switch to release builds for pre-merge by @seldridge in #10150
• [FIRRTL] LowerTypes Wire Domain Association Support by @seldridge in #10151
• [ImportVerilog] Add support for remaining n-input primitives by @TaoBi22 in #10155
• [FIRRTL] InferDomains: insert domain bounce wires by @rwy7 in #10148
• [Synth] Remove MIG support by @uenoku in #10154
• [TruthTable][Synth] Add precomputed 4-input NPN lookup table by @uenoku in #10118
• [Synth] Use truth table merging for cut computation by @uenoku in #10121
• [FIRRTL] Add FIRRTL Exporter Version Support by @seldridge in #10119
• Bump LLVM to e89a4dfabfac7016819d201dacb6c6c58e6a2365 by @mikeurbach in #10047
• FIRRTL] InferDomains: rename classes by @rwy7 in #10157
• [1/4] [MooreToCore] Add stable class object header layout, introduce RTTI slot by @Scheremo in #10127
• [2/4] [MooreToCore] Materialize class RTTI globals by @Scheremo in #10128
• [ImportVerilog] Sort generated modules by source order, deterministically by @jmolloy in #10164
• ImportVerilog: improve testbench compatibility by @AmurG in #10095
• [ImportVerilog] Support using string variables as arguments of $display by @sunhailong2001 in #10147
• [ImportVerilog] Add support for not primitive by @TaoBi22 in #10165
• [FIRRTL][OM] Add property asserts by @seldridge in #10093
• Modify ConvertCombToSynth to run on any op and add unit tests by @joaovam in #10169
• [FIRRTL] Fix C++20 incomplete type error in FIRRTLAnnotationsGen by @ayanbanrj in #10134
• [circt-synth] Add functional reduction conflict limit option by @uenoku in #10170
• [ESI][Runtime] change Verilator cosim flow by @teqdruid in #10159
• [Sim] Add output-stream support and introduce sim.get_file by @nanjo712 in #10163
• [FIRRTL] Remove deprecated printf-encode verif ops by @seldridge in #10173
• [Synth][CutRewriter] Support choice cuts in mapping by @uenoku in #10171
• [FIRRTL][OM] Property Equality Expression by @seldridge in #10168
• [ci] Add z3 to UBTI native builds by @seldridge in #10175
• [SV][ExportVerilog] Add sv.write for no-stream writes by @nanjo712 in #10179
• [ci] UBTI Cleanup by @seldridge in #10177
• [SCFToCalyx] Fix illegal op mutation in RewritePattern by @uenoku in #10178
• [ci] Better release artifact matrix job names, NFC by @seldridge in #10182
• [ci] Restore original buildAndTest job names, NFC by @seldridge in #10183
• [Synth][FunctionalReduction] support for inversion equivalences by @okekayode in #10181
• [LLHD][SV] Unify the ProceduralRegion trait in CIRCTSupport by @fzi-hielscher in #10180
• [Arc] Fix untracked op mutation in canonicalizer by @uenoku in #10176
• [ESI][Runtime] Add SegmentedMessageData to support minimize copies by @teqdruid in #10160
• [Sim] TableGen whistespace cleanup, NFC by @fzi-hielscher in #10196
• [FIRRTL] InferDomains: support probes by @rwy7 in #10167
• [Datapath][Synth] Make comb-to-datapath and lower-word-to-bits work on generic ops by @joaovam in #10198
• [ESI][Runtime] Make esitester public by @teqdruid in #10199
• [ci] Add integration test input to UBTI flows by @seldridge in #10188
• [circt-synth] Reduce problem sizes and load balance LEC tests, NFC by @uenoku in #10202
• [Synth] Add BooleanLogicOpInterface for and_inv by @uenoku in #10190
• [ESI][Runtime] Add UnionType by @teqdruid in #10208
• [ESI][Runtime] Add a workflow to test just the ESI Runtime by @teqdruid in #10209
• [Synth] [LowerWordToBits] Constant defined outside of IsolatedAbove region by @joaovam in #10210
• [SV][HW][Sim] Rework (Non)ProceduralOp traits by @fzi-hielscher in #10195
• [ci] Use UBTI for nightly by @seldridge in #10200
• [Synth] Modify StructuralHash to remove HwModule dependency and add IR test by @joaovam in #10212
• [ESI][Runtime] Fix runtime test workflow by @teqdruid in #10214
• [ESI][Runtime] Update Copilot runtime instructions by @teqdruid in #10220
• [ci] More clang versions in UBTI by @seldridge in #10218
• [ESI][Runtime] Add Window and List types by @teqdruid in #10221
• [Calyx] Fix non-determinism in commonTailPatternWithPar by @uenoku in #10216
• [ExportVerilog] Migrate the tests for sv.fwrite and sv.write to sv-dialect.mlir by @nanjo712 in #10205
• [Synth] Use BooleanLogicOpInterface in LongestPathAnalysis, NFC by @uenoku in #10225
• [Synth][LowerVariadic] Use TypeSwitch over dyn_cast, NFC by @uenoku in #10226
• [ExportVerilog] Update LoweringOptionsParser flags by @Nergy-TCGeneric in #10222
• [Arc] Avoid DenseMap iteration in SplitFuncs by @TaoBi22 in #10228
• [Sim] Add builtin stdout/stderr stream ops by @nanjo712 in #10206
• [ImportVerilog] Add support for buf primitive by @TaoBi22 in #10227
• [Moore][ImportVerilog][MooreToCore] Add DPI call semantics to Moore by @pscabot in #10126
• [Copilot] Move copilot instructions to AGENTS.md files by @teqdruid in #10229
• [Synth] Make MaximumAndCover and FunctionalReduction runnable on any op by @SmitVaishnav in #10211
• [ci] Switch to Clang 19 for Valgrind Nightly by @seldridge in #10219
• [ESI][Runtime] Generate C++ types for windowed lists by @teqdruid in #10224
• [Synth] Refactor invertible logic op handling, NFC by @uenoku in #10232
• [Sim] Implement the lowering logic from sim.proc.print to the SV dialect by @nanjo712 in #10172
• [RTG][circt-tblgen] Use isaMnemonic filed as python function name basis by @maerhart in #10241
• [FIRRTL][SpecializeOption] Allow specialization of non-existent option by @uenoku in #10158
• [Synth][FunctionalReduction] Fix a SSA cycle by @uenoku in #10137
• [github] Add a PR template for AI policy by @uenoku in #10231
• [LLHD] Make Mem2Reg fixpoint iteration deterministic by @fabianschuiki in #10243
• [ESI][Runtime] AGENTS.md: change recommended build method by @teqdruid in #10246
• [docs] Clarifications on AI Tool Use by @seldridge in #10240
• [circt-verilog] Add -Xslang passthrough flag for Slang frontend. by @jpienaar in #10238
• [AIGERImporter] Add AIGER 1.9 support for bad states and invariant constraints by @okekayode in #10244
• [Synth] Add synth.xor_inv by @uenoku in #10233
• [FIRRTL] Add lower-to-core lowering mode by @uenoku in #10162
• [ImportVerilog] Fix slang compilation flag precedence by @fzi-hielscher in #10253
• [FIRRTL] Replace Wires w/ Objects in LowerDomains by @seldridge in #10249
• [ImportVerilog] Add support for pullup/pulldown primitives by @TaoBi22 in #10239
• [SeqToSV] Whitespace test cleanup, NFC by @seldridge in #10259
• [SeqToSV] Fix illegal IR in clock-typed register by @seldridge in #10260
• [slang] Add SLANG_ASSERT_ENABLED=1 for assertion build by @uenoku in #10261
• [ESI][PyCDE] OneItemBufferFromHost channel DMA: Fix buffer issue by @teqdruid in #10247
• [OM] Add debug logging to the Evaluator by @seldridge in #10266
• [OM] Delay assertions until worklist drained by @seldridge in #10267
• [OM][circt-reduce] Add op to unknown reduction by @seldridge in #10271
• [FIRRTL] Name Sanitizer: hierpath, symbol users by @seldridge in #10273
• [Synth] Add StaticInterface for CNF construction, NFC by @uenoku in #10276
• [FIRRTL] Name sanitizer collions, idempotency by @seldridge in #10275
• [ImportVerilog][NFC] Swap primitive tests to use wires by @TaoBi22 in #10257
• [NFC][ImportVerilog] Drop outdated TODO by @TaoBi22 in #10279
• [ESI][PyCDE] Move ESI BSPs into the ESI runtime by @teqdruid in #10281
• [RTG] Add register_to_index and index_to_register ops to visitor by @maerhart in #10280
• [FIRRTL] Don't run MemToRegOfVec on "SeqMem"s by @seldridge in #10284
• [ImportVerilog] Support single-delay case for n-input prims by @TaoBi22 in #10278
• [NFC] Missing requires line in circt-verilog test by @darthscsi in #10290
• [firtool] Fix randomization disable logic by @seldridge in #10285
• [FIRRTL] LowerLayers: Do not include dummy bindfiles by @rwy7 in #10258
• [circt-verilog] Fix failing CI check, NFC by @seldridge in #10292
• [FIRRTL] Remove ReplSeqMem gating of MemToRegOfVec by @seldridge in #10286
• [LLHD] Run Mem2Reg per slot to fix cubic scaling by @fabianschuiki in #10263
• [ImportVerilog] Add support for n-output primitive single delay case by @TaoBi22 in #10289
• [Synth] Add a folder/canonicalization for synth.xor_inv by @okekayode in #10282
• [ImportVerilog] Fix hierarchical name resolution across deduped module instances by @jpienaar in #10255
• Fix n^2 dead code cleanup algorithm by @youngar in #10291
• [Arc] Fix SplitFuncs non-determinism by @TaoBi22 in #10296
• [Synth] Make LowerVariadic run on any operation. by @joaovam in #10242
• [OM] Fix object field value is considered fully evaluated even it's not by @uenoku in #10293
• [OM] Use pass constructors generated by ODS, NFC by @uenoku in #10301
• [OM] Add a folder for IntegerBinaryArithmeticOp and use it in Evaluator, extend StringConcat folder by @uenoku in #10269
• [domaintool] Switch to relationship ClockDomains by @seldridge in #10302
• [PyRTG] Simplify instruction calls by @maerhart in #10252
• Handle alternate form of empty action block. by @jpienaar in #10297
• [PyRTG] More utility methods for instructions by @maerhart in #10272
• circt-bmc: materialize debug anchors by @5iri in #10287
• [ImportVerilog] Add support for $isunknown. by @jpienaar in #10304
• [FIRRTL] InferDomains: drive undriven domain wires by @rwy7 in #10197

New Contributors

• @dmlockhart made their first contribution in #10030
• @ankit-cybertron made their first contribution in #10075
• @Waryc made their first contribution in #10106
• @ayanbanrj made their first contribution in #10134
• @okekayode made their first contribution in #10181
• @Nergy-TCGeneric made their first contribution in #10222
• @SmitVaishnav made their first contribution in #10211

Full Changelog: firtool-1.144.0...firtool-1.145.0