LPS deck not working properly when paired with AI deck

[joatjoses]

I am working on a project using both AI deck and LPS deck and have followed the instructions to move the LPS pins using the patching pads, changed the make menuconfig to use the alternative pins and flashed it, and edited the aideck.c file to set to .usedGpio = DECK_USING_IO_4 and .usedPeriph = 0.

The cfclient console shows that two decks are detected and the aideck can launch then wifi img streamer properly. However, the LPS deck seems to be not working as it cannot detect the anchors which are set to TDoA3 as shown in the image below.

Testing the LPS deck individually shows that it is functional as it can detect the 8 anchors when not paired with the AI deck.

A previous discussion showed that they were able to use both the aideck and LPS properly. Is there some step I have overlooked? Thanks for your help.

[knmcguire]

Hi! I think you didn't do the bridging correctly of GS4. Please see this picture taken from the hyper demo blogpost

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There needs to be a wire to IO4 (see the expansion board pinout)

[knmcguire]

Alzo, you need to use a Stanley knive to physcically cut the GS1 GS2 space between the two solder pads

[joatjoses]

Hello! Thank you for your reply. Will cutting the GS1 and GS2 cause permanent damage or is it reversible? I am borrowing the university's drones and deck and do not want to damage it. I also want to clarify something regarding moving the locopositioning's RST to IO4. The hyper demo blogpost uses the flow deck, loco positioning deck, and lighthouse deck while I am planning to use the AI deck and loco positioning deck. The aideck uses the IO4 for its RST as stated in the deck compatibility. Will it not cause problems if I move the loco positioning's RST to IO4 as well? Another problem that tobbeanton mentioned in this discussion is that the board conflicts on IO1 between aideck's NINA_SYSBOOT and loco's CS. Is there a solution to this?

[knmcguire]

You can reverse it by bridging the solder pads of GS1 and GS2 similarly to what you have done for GS3.

The RST IO4 incompatibility will probably cause an issue.... and the nina being booted as @tobbeanton said will also cause a problem...

I'll discuss this with him and come back to you later.

[knmcguire]

So we noticed that there is an inconsistency in the deck compatibility matrix, since one of the IO2 or IO3 pins is supposed to be shifted (IO3 and IO4). We will check that out later, but yes IO4 will cause issues as Tobias experienced...

@ArtemRedchych seemed to have gotten it to work on that discussion you shared, and we honestly don't know how. Perhaps you can ask in there or he can answer in here?

[sajidj-sketch]

Solved: AI-deck 1.1 + Loco deck fully coexisting (GAP8 + ESP32 WiFi + LPS positioning simultaneously)

Setup: Crazyflie 2.1, AI-deck 1.1, Loco deck, crazyflie-firmware 2025.02 (d89b0c7a).
Result: both decks enumerate and run at once — GAP8 app running, ESP32 up with WiFi (CPX intact), LPS ranging + position estimate valid. Unlike the earlier .usedPeriph = 0 workaround in this thread, the ESP32 stays fully functional.

1. Pin conflict map (AI-deck 1.1 datasheet Rev 2, §3)

Pin	AI-deck	Loco (stock)	Resolution
RX1/TX1	UART1 → GAP8	IRQ / RST (GS1/GS2)	cut GS1+GS2, reroute
IO1	ESP32 SYSBOOT (strap, sampled at ESP32 reset release)	SPI CS (fixed, not routable)	share (safe — see §2)
IO2	—	alt IRQ	use for IRQ
IO3	—	alt RST	use for RST
IO4	reset to both GAP8 and ESP32	—	never route Loco RST here
RX2/TX2	UART2 → ESP32 (CPX/WiFi)	—	keep UART2 in firmware

2. Why Loco RST on IO4 kills the ESP32 (deterministic, not a race)

locodeck.c init does, in this order:

pinMode(CS_PIN, OUTPUT);          // CS = IO1: STM32 output register defaults to 0
                                  // → IO1 drives LOW; first SPI txn (raising CS) is later
digitalWrite(GPIO_PIN_RESET, 0);  // 10 ms reset pulse
vTaskDelay(M2T(10));
digitalWrite(GPIO_PIN_RESET, 1);  // release → ESP32 samples SYSBOOT (= IO1 = LOW) NOW

If RST is on IO4, the pulse resets GAP8+ESP32; the ESP32 leaves reset with SYSBOOT low → enters ROM serial bootloader → app never runs. Symptom: GAP8 LED blinks, ESP32 LED dead, no WiFi; remove the LPS deck and the ESP32 is fine. GAP8 survives because its boot straps are not on IO1. With RST on IO3 the Loco never resets the ESP32, and IO1 sharing is harmless (SYSBOOT only sampled at reset release).

3. Hardware rework (Loco deck only; AI-deck untouched)

1. Cut GS1, GS2 (frees RX1/TX1 → UART1 for GAP8)
2. Bridge GS3 (IRQ → IO2)
3. Wire DWM1000 RST → IO3 (not IO4)

Final: CS=IO1, IRQ=IO2, RST=IO3.

Continuity checks, power off (IO3/IO4 are adjacent holes — a stray bridge here reproduces the IO4 failure exactly; it bit me):
RST↔IO3 beeps · RST↔IO4 silent · IO3↔IO4 silent · IRQ↔IO2 beeps · CS↔IO1 beeps.

4. Firmware changes (3 items)

(a) Kconfig (make menuconfig → Expansion deck configuration):

CONFIG_DECK_LOCODECK_USE_ALT_PINS=y        # IRQ=IO2, RST=IO3
# CONFIG_LOCODECK_ALT_PIN_RESET is not set # must stay OFF — ON selects IO4

plus your WiFi setup (CONFIG_DECK_AI_WIFI_SETUP_STA=y or _AP=y, CONFIG_DECK_AI_SSID, CONFIG_DECK_AI_PASSWORD). ⚠ make cf2_defconfig silently resets all of these.

(b) src/deck/drivers/src/aideck.c — release IO1 to the Loco (resource manager otherwise refuses to init the second deck; both drivers declare IO1). Keep IO4 and UART2:

-    .usedGpio = DECK_USING_IO_1 | DECK_USING_IO_4,
+    .usedGpio = DECK_USING_IO_4,
     .usedPeriph = DECK_USING_UART2,   // keep! UART2 carries CPX/WiFi; 0 kills the ESP32 link

Safe because the driver only toggles IO1/IO4 during deliberate ESP32 re-flashing over CPX (resetEspToBootloader()), not in normal operation.

(c) src/deck/drivers/src/locodeck.c — make CS idle high before the DW1000 reset pulse. Correct SPI hygiene, and closes the §2 trap even if the reset lines are ever tied together again (design or solder bridge):

   // Init pins
+  digitalWrite(CS_PIN, 1);   // pre-load ODR: pin comes up driving HIGH, no low glitch
   pinMode(CS_PIN, OUTPUT);
   pinMode(GPIO_PIN_RESET, OUTPUT);
   pinMode(GPIO_PIN_IRQ, INPUT);

5. Build & flash

make menuconfig          # options from 4(a)
make -j$(nproc)          # → build/cf2.bin
make cload               # or: make cload CLOAD_CMDS="-w radio://0/80/2M"

6. Verify

• Console: both decks init, no resource conflict/assert
• GAP8 LED blinks; ESP32 LED blinks, WiFi up (I stream from a custom ESP32 UDP firmware)
• LPS ranging active, valid position estimate

7. Caveats

• Don't re-flash ESP32/GAP8 over CPX while the Loco is active — that path drives IO1 (SYSBOOT) and IO4, which now interact with the running Loco. Detach the LPS deck for AI-deck firmware updates.
• IO1 remains physically shared (CS vs SYSBOOT); with fix 4(c) the boot window is closed and runtime CS traffic is harmless.
• Only IO2/IO3 are free alongside the AI-deck — this rework consumes both, so it won't stack with decks needing IO2/IO3 (e.g. flow deck's IO3) without further patching.