Add multi-group support for CachePool

[DiyouS]

Summary

Extends CachePool from a single group of tiles to a configurable 2D mesh of groups, each connected via a FlooNoC-based inter-group
interconnect, plus a matching L2 refill mesh and a hardware partial-barrier mechanism scoped to individual tiles.

Multi-group cluster architecture

• New hierarchy level: Cluster → Group × N (FlooNoC 2D mesh) → Tile × M → Core Complex + L1 cache. Groups are arranged in an X×Y mesh
  (num_groups_x/num_groups_y), each exposing per-tile NoC ports ("planes") that connect directly to the corresponding plane on
  X/Y-neighboring groups.
• Tile IDs are globally unique and flat (tile_id = tile_base_id + t = (gy*NumGroupsX + gx) * NumTilesPerGroup + t), so a tile's group can
  be recovered directly from the upper bits of its ID.
• cachepool_group_noc_wrapper handles the inter-group boundary per group: a per-tile concentration crossbar, a floo_router pair (request +
  response) per tile/plane, and a group-wide dispatch crossbar back into the tile's local remote ports.
• Each tile's TCDM crossbar (tcdm_cache_interco) now does 3-way routing per request: local cache bank, intra-group remote (same group,
  different tile), or inter-group remote (different group) — selectable per-config via num_rg_ports_per_core; setting it to 0 disables all
  multi-group RTL and falls back to single-group behavior.
• BootROM and the refill crossbar moved to group level to scale with group count.

L2 refill NoC

• Replaces the previous point-to-point L2/DRAM refill path with a TCDM-based mesh spanning groups, so every group can reach every L2/HBM
  channel regardless of physical placement in the mesh.
• Per-group reqrsp_to_axi conversion happens before the mesh hop, with a group-count-aware AXI mux stage merging traffic onto the shared
  wide AXI ports.

Partial barrier (tile-level, direct-wire)

• New direct-wire cluster barrier (cachepool_cluster_barrier) that collects per-tile barrier requests and broadcasts completion, replacing
  a full-cluster-only barrier with one that supports excluding tiles via a runtime-configurable participation mask.
• Participation mask is software-writable through a new peripheral CSR (HW_BARRIER_PARTICIPATION_MASK, multi-word to scale past 32 tiles)
  and exposed to the runtime via snrt_barrier APIs, so a kernel can synchronize a subset of tiles instead of the whole cluster.
• New partial_barrier and partial_barrier_benchmark test kernels; the existing multi-producer/consumer RLC kernel was adapted to use it.

NoC visualization / profiling

• Cycle-accurate per-router/tile/core NoC traffic logging (hardware/tb/cachepool_noc_profiling.sv), opt-in via noc_profiling=1, consumed
  by util/scripts/noc_profiling_to_vis4mesh.py to render mesh traffic heatmaps (see README's "NoC Visualization" section).

New configs

• cachepool_fpu_4g (2×2 mesh), cachepool_fpu_16g / cachepool_fpu_16g_tiny (4×4 mesh) alongside the existing single-group configs.

TODOs

• Pass lint checks (Ongoing)
• Fix a bug in rsp fifo handling
• Fix the waveform script for cache controller
• Add new scoreboard system in interconnection for debugging