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@github-actions github-actions released this 13 May 05:01
· 36 commits to main since this release
v0.9.8
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Learn about vigilant mode.

Notable changes in the RISC-V CHERI specification since v0.9.7.1

These changes were made based on ARC review feedback on the previous version:

  • New Opcode Allocation:
    • Relocated instruction encodings from the standard RISC-V opcode space to formerly Custom space. Custom1-3 become reserved for RVY when the base ISA is RVY, all new instructions are in what is Custom-3 for RVI.
    • Change the immediate format of YBNDSWI
    • Added scripts to generate Sail, QEMU, and riscv-opcodes clauses, and new appendices for encoding overviews and standalone documentation references.
  • Clarified Hybrid Mode:
    • Hybrid Mode Rewrite: Substantially cleaned up the hybrid mode definition and now use the name P-bit (instead the M-bit) for controlling pointer modes
    • Zyhybrid is now defined as an extension on top of the RVY base ISA rather than RVI, maintaining identical functionality while aligning with the new encoding structure (cannot be based on RVI otherwise RVY opcode space would be custom).
    • Added a new appendix detailing intended hybrid usage models.
  • Zylevels1 (Local/Global) Rewrite: Substantially refactored the Zylevels1 chapter to simplify it and add usage examples.
  • Further ARC Review Updates:
    • Integration of the YBLD and YTOPR instructions into the base ISA to avoid single-instruction extensions.
    • Fixed name of YLT (it's an inclusive subset not a less than) to use YSS (for subset)
    • Many other smaller improvements based on ARC feedback (full list of changes below).

Spec changes

Documentation updates

System updates

New Contributors

Full Changelog: v0.9.7.2...v0.9.8

Contributors

DaveMcEwan, arichardson, and 3 other contributors
Assets 14
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