Architecture

Architecture

Generated with Grok Build: Grok 4.5 · xAI Imagine (/imagine)

Placement

training / runtime crates  (float thresholds, weights, decay)
              │
              ▼
        silicon-bridge   ──.mem / UART──►  silicon-hdl (FPGA RTL)

Host-side deployment layer: encode, file I/O, optional UART, timing metrics.

Owns

• Unsigned Q8.8 encode/decode helpers and parameter bundles
• Vivado $readmemh .mem generation
• Export trait surface for silicon-hdl alignment
• UART host client (feature-gated)
• WNS parsing for CI gates

Does not own

Area	Owner
Neuron dynamics	neuromod
Spike encoding	axon-encoder
MoE extract	engram-parser
Training	plasticity-lab
Reward	limbic-critic
Daemon lifecycle	brainstem-daemon
SystemVerilog / Vivado projects	silicon-hdl
NIR HDF5 I/O	nir-rs (future consumer, not reimplemented here)

Provenance

Extracted from private Eagle-Lander neuromorphic supervisor; FPGA export path open-sourced for any SNN float parameters.

Related

• Boundary Matrix
• Ecosystem

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: de069cd (main)