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🎉 Two years NEORV32! 😄

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ℹ️ See CHANGELOG.md for more details.

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  • [Zxcfu ISA ext.] add option to implement custom RISC-V instructions by @stnolting in #264
  • 🐛 [sw] fixed bug in bootloader's (M)TIME handling by @stnolting in #267
  • 🧪 Using LTO (link-time-optimization) for bootloader + console improvements by @stnolting in #268
  • [docs/datasheet] rework & update NEORV32 runtime environment (RTE) section by @stnolting in #272
  • [rtl] add err_o signal to IMEM modules by @stnolting in #273
  • [rtl] on-chip debugger: add RISC-V trigger module for hardware breakpoints by @stnolting in #274
  • [sw] add support for newlib's system calls by @stnolting in #275
  • ⚠️ replace SYSINFO.CPU memory-mapped register by custom "mxisa" CSR by @stnolting in #276
  • [OCD] stop CPU counters during debugging by @stnolting in #277
  • Add newlib example program and documentation by @stnolting in #278

Full Changelog: v1.6.7...v1.6.8

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  • [setups] move to repo neorv32-setups by @umarcor in #254
  • [rtl/core] rework CPU issue engine (area optimization) by @stnolting in #256
  • [DOC] User Guide - 1.3. Installation by @befedo in #258
  • [B ISA extension] add single-bit instructions (Zbs) support by @stnolting in #259
  • [B ISA extension] add carry-less multiply instructions (Zbc) support by @stnolting in #260
  • [CFS] add demo program by @stnolting in #261
  • [rtl/core] add 4 additional CPU CP slots; fix bugs in CP arbitration logic by @stnolting in #262
  • [sw] rework intrinsics (e.g. for custom instructions) by @stnolting in #263

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Full Changelog: v1.6.6...v1.6.7
Project Changelog: CHANGELOG.md

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