Releases: stnolting/neorv32
Releases · stnolting/neorv32
v1.10.5
What's Changed
- [rtl] signal renamings and cleanups to make the code more readable by @stnolting in #1026
- 🐛 fix minor bug in FPU MUL instruction by @stnolting in #1028
- [rtl] remove redundant
prog_buf
by @NikLeberg in #1030 - [rtl] fix generate spelling by @NikLeberg in #1031
- [cpu] rework ALU instruction decoding and CPU co-processor interface by @stnolting in #1032
- ✨ [cpu] add support for RISC-V scalar cryptography ISA extensions by @stnolting in #1033
- Fix typo trap table by @BEforlin in #1035
- Add Zkt ISA extension by @stnolting in #1036
- ✨ add support for RISC-V
Zbkb
ISA extension by @stnolting in #1037 - ✨ add support for RISC-V
Zbkc
ISA extension by @stnolting in #1038 - Add
Zkn
ISA extension by @stnolting in #1039 - ✨ add support for RISC-V
Zks*
ISA extensions by @stnolting in #1040 ⚠️ Rename CPU ISA configuration generics by @stnolting in #1041⚠️ split B ISA extension into individual sub-extensions by @stnolting in #1044
New Contributors
Full Changelog: v1.10.4...v1.10.5
v1.10.4
What's Changed
- minor RTL cleanups and optimizations by @stnolting in #1004
- 🧪 Remove "loop" from memory initialization function by @stnolting in #1005
- minor fixes in OCD by @NikLeberg in #1006
- [sw] fix
sysinfo
doxygen header by @NikLeberg in #1007 - optimize CSR address logic by @stnolting in #1008
- Minor rtl/CSR optimizations by @stnolting in #1010
- Cleanup debug symbols by @stnolting in #1009
- minor HDL cleanups and otimizations by @stnolting in #1014
- Cleanup and extend watch dog's reset-cause logic by @stnolting in #1015
⚠️ Refactor RTL files / hierarchy by @stnolting in #1017- 🐛 fix B.CTZ decoding regression bug by @stnolting in #1018
- Massive rtl code cleanup by @stnolting in #1019
- 🐛 fix stack alignment upon first procedure entry by @stnolting in #1021
Full Changelog: v1.10.3...v1.10.4
v1.10.3
What's Changed
⚠️ rework CFU (remove R5-type instructions) by @stnolting in #971- Rework (and auto-generate) file-list files by @stnolting in #972
- [docs] fix spelling by @NikLeberg in #975
- [vivado_ip] fix error when AXI port is unconnected by @stnolting in #976
- [vivado_ip] fix unconnected variable-size inputs by @stnolting in #978
- [vivado_ip] constrain minimal size of variable-sized output ports by @stnolting in #980
- Minor RTL edits by @stnolting in #984
⚠️ reorganize core RTL files⚠️ by @stnolting in #985- [rtl] minor timing and area optimizations by @stnolting in #990
- RTL reworks, cleanups and optimizations by @stnolting in #996
- 🐛 fix minor regression bug; minor RTL optimizations by @stnolting in #998
Full Changelog: v1.10.2...v1.10.3
v1.10.2
What's Changed
- minor software framework cleanups and optimizations by @stnolting in #940
- minor rtl cleanups and optimizations by @stnolting in #941
- minor rtl edits by @stnolting in #948
- [image_generator] add *.mif memory initialization file format by @stnolting in #949
- Add option to disable SYSINFO module by @stnolting in #952
- 🐛 Fix SDI "TX FIFO full" flag by @stnolting in #953
- [SPI] add programmable chip-select operations by @stnolting in #954
- Minor SDI edits by @stnolting in #955
- 🐛 [newlib] fix broken
sbrk
function by @stnolting in #957 - [rtl] clean-up simulation-only pragmas by @stnolting in #956
- 🔒 restrict access to IO modules to privileged (machine-mode) software by @stnolting in #958
- Minor SW framework edits to fix c++ warnings by @stnolting in #964
- Make SYSINFO CLK writable by @stnolting in #966
Full Changelog: v1.10.1...v1.10.2
v1.10.1
What's Changed
⚠️ remove redundant JTAG reset signal (TRST) by @stnolting in #928- minor rtl code clean-ups by @stnolting in #929
- Add UART FIFO clear flags; add DMA FIRQ interrupt configuration by @stnolting in #930
- Minor rtl edits/cleanups by @stnolting in #931
⚠️ rework CFU interface by @stnolting in #932- minor software updates and fixes by @stnolting in #933
- [sw] add auxiliary/helper functions library by @stnolting in #934
- minor rtl edits and cleanups by @stnolting in #935
- Minor sw & hw cleanups by @stnolting in #936
- 🧪 Add experimental XBUS (Wishbone) to AHB3-Lite bridge by @stnolting in #937
⚠️ Remove AMO_RVS_GRANULARITY generic by @stnolting in #938⚠️ rework GPTMR by @stnolting in #939
Full Changelog: v1.10.0...v1.10.1
v1.10.0
What's Changed
- Add NEORV32 as Vivado IP by @stnolting in #894
- Cleanup SW library by @stnolting in #900
- Add back Dhrystone port by @stnolting in #901
- Update neorv32_sdi.vhd - Minor typo correction by @ucycg in #903
- Add COE and MEM file generator options by @stnolting in #904
- [FPU] prevent GCC from emitting fused multiply-add instructions by @stnolting in #905
- Add SLINK routing information ports by @stnolting in #908
- Make XIRQ trigger configuration programmable by @stnolting in #911
- Add HDL file list files by @stnolting in #909
- Relocate f files by @stnolting in #912
- Add variable-sized ports to Vivado IP block by @stnolting in #913
- Fix uncached/cached access priority by @stnolting in #915
- [xbus] access type identifier (tag signal) by @stnolting in #917
- [sw/lib]
⚠️ rework gpio_pin_set function by @stnolting in #921 - [rtl] TRNG: add data-available interrupt by @stnolting in #922
- Minor code cleanups by @stnolting in #925
- ✨ Add pre-configured Eclipse example project by @stnolting in #926
New Contributors
Full Changelog: v1.9.9...v1.10.0
v1.9.9
What's Changed
- minor rtl clean-ups and optimization by @stnolting in #872
- use simplified VHDL file headers by @stnolting in #873
⚠️ rename SLINK data interface registers by @stnolting in #874⚠️ simplify XBUS gateway by @stnolting in #876- [DMA] use FIRQ select instead of FIRQ mask by @stnolting in #877
- rtl logic optimization and cleanups by @stnolting in #880
- fix external debug-halt vs. exception concurrency by @stnolting in #882
- minor rtl fixes by @stnolting in #883
- [rtl] fix single-step halting by @stnolting in #887
- minor rtl cleanups by @stnolting in #889
- Fix UART receiver by @Unike267 in #891
Full Changelog: v1.9.8...v1.9.9
v1.9.8
What's Changed
- CPU RTL optimization by @stnolting in #857
⚠️ remove WDT + TRNG interrupts; 🐛 fix bug in core-complex clocking during sleep by @stnolting in #858⚠️ rework ONEWIRE and GPTMR interrupts by @stnolting in #859⚠️ rework TWI interrupt by @stnolting in #860- 🐛 fix DMA fence flag,
⚠️ rework CPU FIRQs by @stnolting in #864 - Support tool-specific standard flags in makefile by @jpf91 in #862
⚠️ rework TWI module by @stnolting in #865- add back TWI clock stretching option by @stnolting in #867
- [SLINK] split interrupt into two FIRQs by @stnolting in #868
- B ISA extensions only contains Zba + Zbb + Zbs by @stnolting in #869
- add additional SPI and SDI interrupt conditions by @stnolting in #870
Full Changelog: v1.9.7...v1.9.8
v1.9.7
What's Changed
- [rtl] add generic cache module (not used yet) by @stnolting in #842
- rtl cleanups and optimizations by @stnolting in #843
⚠️ remove Wishbone tag signal by @stnolting in #845⚠️ ⚠️ Rename external bus interface by @stnolting in #846- ✨ Add optional external bus interface cache (XCACHE) by @stnolting in #849
⚠️ processor configuration edits / clean-ups by @stnolting in #850- Minor cache updates by @stnolting in #851
- [litex] update core complex wrapper by @stnolting in #852
- rework cache system by @stnolting in #853
- Connected SPI bus to on-board Flash and SPI peripheral by @lovelesh-mis in #854
- Update CFU example: use XTEA as "real world" demo application by @stnolting in #855
- Updated Performance test by @mikaelsky in #844
New Contributors
- @lovelesh-mis made their first contribution in #854
Full Changelog: v1.9.6...v1.9.7
v1.9.6
What's Changed
- Allow disabling certain PMP modes by @stnolting in #808
- [revert] remove page faults support by @stnolting in #809
- 🐛 Fix bug in CRT0 trap handler by @stnolting in #812
⚠️ Rework hardware performance monitor (HPM) events by @stnolting in #811- 🧪 [makefile] pass CC_OPTS variable as define string by @stnolting in #813
⚠️ remove Smcntrpmf ISA extension by @stnolting in #814- [sim] add simulation check to sw makefiles as target 'sim-check' by @umarcor in #817
- [SLINK] add AXI-stream-compatible "tlast" signals by @stnolting in #815
- [docs/userguide/simulating_the_processor] add admonition and recommend MARCH=rv32im to build hello_world by @umarcor in #819
- [ci] split SoftwareFrameworkTests from simple testbench simulation by @umarcor in #820
- 🐛 Fix write access to mip.firq CSR bits by @stnolting in #821
- [ci] test example hello_world as well by @umarcor in #822
- [fifo] fix (Vivado) synthesis issue by @stnolting in #827
- optimize FIFO component to improve mapping by @stnolting in #828
- Added dummy clocks for SLINK streams in AXI4-Lite wrapper by @robhancocksed in #831
- 🐛 fix atomic write/clear/set accesses of clear-only CSR bits by @stnolting in #829
- [sw] remove unused variable RISCV_TOOLCHAIN by @umarcor in #832
- 🐛 fix GPTMR threshold = 0 configuration by @stnolting in #834
- Small correction in user guide by @davidgussler in #835
New Contributors
- @robhancocksed made their first contribution in #831
- @davidgussler made their first contribution in #835
Full Changelog: v1.9.5...v1.9.6