Initial design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
-
Updated
Feb 20, 2018 - Verilog
Initial design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
NVDLA small config implementation on Zynq ZCU104 (evaluation)
RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
FAST-9 Accelerator for Corner Detection
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
Template for project1 TPU
Convolutional accelerator kernel, target ASIC & FPGA
CNN hardware accelerator to accelerate quantized LeNet-5 model
Projects of the digital logic design lab (Fall01) at the University of Tehran.
Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
Add a description, image, and links to the accelerator topic page so that developers can more easily learn about it.
To associate your repository with the accelerator topic, visit your repo's landing page and select "manage topics."