Template for project1 TPU
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Updated
May 1, 2021 - Verilog
Template for project1 TPU
Convolutional accelerator kernel, target ASIC & FPGA
FAST-9 Accelerator for Corner Detection
NVDLA small config implementation on Zynq ZCU104 (evaluation)
RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
Initial design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
Projects of the digital logic design lab (Fall01) at the University of Tehran.
CNN hardware accelerator to accelerate quantized LeNet-5 model
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