altera
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DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
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Apr 8, 2024 - SystemVerilog
Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.
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Mar 28, 2020 - SystemVerilog
SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.
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Sep 5, 2021 - SystemVerilog
A Tic-Tac-Toe with multiple level levels and flashing lights implementation using Hardware Definition Language (Verilog) and DE10-Lite Altera Max 10 FPGA.
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Mar 9, 2018 - SystemVerilog
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