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axi4

Here are 10 public repositories matching this topic...

WangXuan95 / FPGA-DDR-SDRAM

An FPGA-based AXI4 DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

fpga controller rtl verilog soft-core axi4 ddr-sdram ddr1

Updated Sep 15, 2023
Verilog

ultraembedded / core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer

video fpga verilog framebuffer hdmi dvi xilinx-fpga axi4

Updated Aug 9, 2020
Verilog

ultraembedded / core_dbg_bridge

UART -> AXI Bridge

fpga verilog uart axi4

Updated Jul 1, 2021
Verilog

ultraembedded / core_spiflash

SPI-Flash XIP Interface (Verilog)

fpga verilog spi spi-flash xip axi4

Updated Oct 24, 2021
Verilog

ultraembedded / core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

fpga verilog ftdi communications-blocks ftdi-232h axi4

Updated Jun 5, 2021
Verilog

yohanes-erwin / zynq7000

[Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol

zybo zynq-7000 axi4

Updated Feb 22, 2020
Verilog

DOUDIU / Video-Stitching

This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.

real-time fpga video-stitching axi4 read-write-ddr

Updated Oct 28, 2024
Verilog

rlee287 / hardware-bus-infrastructure

A collection of formal properties for hardware buses, and cores using them.

psl sva wishbone-bus axi4 axi4-lite axi4-stream bus-standards

Updated Feb 22, 2021
Verilog

sarthi92 / boron_codesign

ZYNQ7 FPGA Co-design of BORON Cipher

c fpga verilog codesign zynq-7000 axi4

Updated Nov 17, 2018
Verilog

Ammar-Bin-Amir / AXI4

RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle

verilog axi4 rtl-design bus-protocol axi4-lite-interface handshaking-algorithm

Updated Apr 7, 2024
Verilog

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