一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

HDL support for VS Code

Bluespec System Verilog language extension for Visual Studio Code

Bluespec SystemVerilog Package for Sublime Text

Domain Specific Hardware Accelerators - VLSI CAD Project

Bluespec SystemVerilog extension for VS Code

Forth CPU J1 in Bluespec SystemVerilog (BSV)

Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)

Bluespec implementation of PG routing algorithm on a network on chip running a SMIPS

🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn. 适用于BSV中文教程的Docker BSV （WSL2）环境。

A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance

Bluespec System Verilog syntax highlighting for Notepad++

Implementação do protocolo TCP para a disciplina de Redes de Computadores da Universidade Federal de São Carlos - UFSCar

To toy around with Bluespec-SystemVerilog and my Basys3 board

Wishbone/Bluespec Systemverilog Transactors

Hardware implementation of floating point unit (IEEE-754 compliant) for RISC-V architecture

FSM coding styles in BSV

Learning bluespec with bunch of tutorials and example codes