comparch

Here are 3 public repositories matching this topic...

ayandeephazra / Computer_Architecture_and_Verilog

Compilation of my Computer Architrcture and Verilog Courses at UW. Documentation for the code included in the individual directories.

fpga verilog comp comparch

Updated Feb 14, 2023
Verilog

arnavvermagit / rv32i-pipelined-cpu

Star

32-bit 5-stage pipelined RISC-V CPU (RV32I) in Verilog HDL. Supports ADD, SUB, AND, OR, LW, SW, BEQ, BNE with hazard handling (forwarding, stalls, flushes). Verified using testbenches and GTKWave, achieving CPI ≈ 1.0 on hazard-free execution.

riscv verilog comparch rv32i digitaldesign cpu-design 5stagepipeline

Updated Sep 24, 2025
Verilog

Polaris000 / CS_F342

Star

Lab assignments and some practise done for the Computer Architecture course at BITS Pilani

assembly labs verilog practise computer-architecture comparch bits-pilani

Updated Nov 10, 2019
Verilog

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