Simple Computer Architecture using direct mapped cache memory. Designed in VHDL and Quartus.
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Jun 30, 2020 - VHDL
Simple Computer Architecture using direct mapped cache memory. Designed in VHDL and Quartus.
A processor built using VHDL that can execute assembly/machine codes.
A digital design project for a MIPS Reduced Instruction Set Computer (RISC) single-cycle processor design that supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL
Mano computer implementation in VHDL - Computer Architecture course project.
IITB-RISC is a 16-bit very simple computer developed for the teaching that is based on the Little Computer Architecture.
Simple MIPS 16-bit CPU implemented in VHDL with an assembler in python
A 16-bit multi-cycle processor described in VHDL and implemented on an FPGA
This repository contains all my VHDL codes and projects. Feel free to use them however you like. I hope that you like them and that you find them educational/helpful. Feel free to connect with me on LinkedIn!
A Multicycle implementation of the MIPS instruction set architecture using VHDL
Computer Architecture Lab
Computer Architecture practice using VHDL.
Hardware Accelerator design for Euler and Modified method in solving ODE using VHDL language in Xilinx Vivado Environment
Course Project for EE224 (Digital Systems) offered in Autumn 2023
16 Bit, multicore, unicycle processor for general purpose simulated in VHDL. Created as a tool for teaching computer architecture at Federal University of Piauí.
Computer Architecture course project - ECE, Technical University of Crete
Computer Architectures project to design a 16/32 bit microprocessor in VHDL.
IITB-RISC is a six stage pipelined processor described in VHDL and implemented on an FPGA
MyRISC is an educational processor based on the MIPS architecture.
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