A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Updated
May 16, 2024 - SystemVerilog
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
An open source, parameterized SystemVerilog digital hardware IP library
SystemVerilog examples for a digital design course
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
Term project for CS223 Digital - Design course.
MIPS written in System Verilog
Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
Minimalistic RV32I RISC-V Processor in System Verilog
Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.
Cuarto laboratorio del curso de Taller de Diseño Digital. La idea es generar un código compilable para una FPGA con la que se pueda simular el funcionamiento de máquina de café utilizando el lenguaje de programación SystemVerilog.
Moore.io Demo Project
A single cycle processor implementing a subset of the ARMv7 ISA.
Compare the speeds of the Carry ripple adder and Carry-lookahead adder
This is a repo where I share the System Verilog exercises that I worked on. Contributions and suggestions are welcome
UART Transmitter and Receiver implementation for FPGA
Project assigned in the CS223 - Digital Design course at Bilkent University. (2017-2018)
A simple Floating-Point arithmetic unit - implemented in SystemVerilog
🖥️ Digital Design and Computer Architecture
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