digital
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A multiplier which takes two 4-bit operands in and returns the corresponding 8-bit product.
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Oct 2, 2017 - Verilog
A repository of my Lattice MachXO2 FPGA, using a STEP MaxhXO2 development board v2.2
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Oct 29, 2018 - Verilog
A digital genetic algorithm processor
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Apr 10, 2020 - Verilog
Digital Electronics Course Projects
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Jun 7, 2020 - Verilog
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
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Dec 11, 2020 - Verilog
These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA
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Jan 11, 2021 - Verilog
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May 31, 2021 - Verilog
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
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Jun 1, 2021 - Verilog
In electronics, a multiplexer (or mux; spelled sometimes as multiplexer, also known as a data selector, is a device that selects between several analog or digital input signals and forwards the selected input to a single output line.
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Jul 24, 2021 - Verilog
A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.
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Jul 25, 2021 - Verilog
This repository highlghts the manual design of datapath and control path with ASMD Chart and its comparison with the synthesis from behavior level RTL and finally the synthesised design is mapped to the Skywater130nm standard cells and Netlist is generated
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Jul 26, 2021 - Verilog
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