CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
-
Updated
Nov 25, 2019 - SystemVerilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Single-Cycle RISC-V Processor in systemverylog
simple read/write pcap tasks for SystemVerilog test
CAPIPrecis a Coherent Accelerator Processor Interface (CAPI) Abstract Layer
SublimeText3 bits for Quartus, ModelSim, and VUnit Integration mirror of https://phabricator.kairohm.dev/diffusion/10/
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL
Scrolling Display Implemented With Digital Design Concepts on De1-SoC
Computer Architecture Lab - Assignments - Fall 2023
Pipeline Processor based on RISC-V, implemented forwarding and hazard detection units
This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
FPGA stuff
Add a description, image, and links to the modelsim topic page so that developers can more easily learn about it.
To associate your repository with the modelsim topic, visit your repo's landing page and select "manage topics."