An automatic traffic light controller is designed and simulated using the concept of Finite State Machine in ModelSim.
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Updated
Jul 27, 2020 - Verilog
An automatic traffic light controller is designed and simulated using the concept of Finite State Machine in ModelSim.
Verilog Programs
A Verilog-based state machine module for managing resource arbitration among multiple requesters in a synchronous digital system.
Курс по программированию ПЛИС с примерами
Computer architecture course team project
My Digital Logic course project - Elevator state machine
Simulation of logic circuits using Verilog, Proteus and other tools.
Digital systems class at uni
The project below orients the likes of Verilog, Intel Quartus Prime, and DE1_SoC boards to compute a combination lock through Moore FSM applications!
Simulate a statement through Moore FSM, With a full explanation. This project was my last additional course project for Verilog in Digital Systems Design during my BS in Computer Engineering
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