CUGR, VLSI Global Routing Tool Developed by CUHK
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Updated
Feb 27, 2023 - C++
CUGR, VLSI Global Routing Tool Developed by CUHK
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
Design, layout, and simulation files of the paper "Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface" by M. Walter, J. Croshaw, S. S. H. Ng, K. Walus, R. Wolkow, and R. Wille in DATE 2024.
Physical Design (2020 Spring)
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