RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Custom processor implemented in logisim-evolution

18-bit processor implementation using Logisim

CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations