processor-design
Here are 16 public repositories matching this topic...
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
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Jul 17, 2022 - Verilog
EE577b-Course-Project
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May 6, 2020 - Verilog
Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design
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Nov 28, 2018 - Verilog
A simple processor designed using Verilog and Altera DE1 development board.
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Apr 22, 2020 - Verilog
MIPS Multicycle CPU design in Verilog
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Jan 30, 2022 - Verilog
FPGA implementation of a special purpose processor that performs single operation using custom ALU. You can take look at the [related blog post] (https://overengineer.github.io/SpecialPurposeProcessor) for further details.
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Jan 3, 2019 - Verilog
It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.
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Dec 5, 2023 - Verilog
A synthesizable pipelined RISC-V processor. (Digital System Design, Spring 2020, NTUEE)
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Jul 20, 2020 - Verilog
Designed the revised single-cycle datapath and revised control units which make a processor that executes the instructions as well as the instructions implemented already in the design.
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Jun 7, 2022 - Verilog
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Feb 2, 2021 - Verilog
Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA
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Aug 6, 2023 - Verilog
Pipelined MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad
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Nov 18, 2023 - Verilog
Multi-core Processor Design for Matrix Multiplication Using Verilog
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Dec 20, 2021 - Verilog
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