A VHDL implementation of a RISC-V model processor
-
Updated
Jul 15, 2023 - VHDL
A VHDL implementation of a RISC-V model processor
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
Implementação VHDL de um processador de ciclo único com suporte a um subconjunto de instruções ARMv8.
First project to INP - create processor what accepts brainfuck as its instructions
A 5-stage pipelined processor with its own ISA and assembler implemented in VHDL. Link to the schematic diagram:
MyRISC is an educational processor based on the MIPS architecture.
Computer organisation and architecture assignments
16-bit MIPS Processor from scratch in VHDL
A pipelined unit designed in VHDL that can execute Intel MMX instructions, as well as an assembler written in C++
Digital design and synthesis of a DLX processor in VHDL
ISA extension of Ibex core for ASCON lightweight cryptography algorithm
Add a description, image, and links to the processor topic page so that developers can more easily learn about it.
To associate your repository with the processor topic, visit your repo's landing page and select "manage topics."