A semester-long design of pipeline arm processer using RISC instruction set.
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Updated
Jun 6, 2022 - C
A semester-long design of pipeline arm processer using RISC instruction set.
Code Repository of Assignments done as part of Computer Architecture Lab course at IIT Kharagpur
Functional/Pipeline Simulator for simpleRISC processor
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SISA Architecture Emulator
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Small Processing Unit 32: A compact RV32I CPU written in Verilog
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