Here are
17 public repositories
matching this topic...
Neural Turing Machine for a System on Chip verified with UVM/OSVVM/FV
Updated
Jun 3, 2024
SystemVerilog
System on Chip verified with UVM/OSVVM/FV
Updated
Jun 3, 2024
SystemVerilog
System on Chip with RISCV-32 / RISCV-64 / RISCV-128
Updated
Jun 3, 2024
SystemVerilog
System on Chip with OpenRISC-32 / OpenRISC-64
Updated
Jun 3, 2024
SystemVerilog
System on Chip with MSP430-16
Updated
Jun 3, 2024
SystemVerilog
An AXI4 crossbar implementation in SystemVerilog
Updated
May 28, 2024
SystemVerilog
🌌 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
Updated
May 17, 2024
SystemVerilog
Notes after working with Zynq platform using vivado and petalinux
Updated
Feb 26, 2024
SystemVerilog
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
Updated
Sep 14, 2023
SystemVerilog
Updated
Sep 4, 2023
SystemVerilog
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
Updated
Aug 28, 2023
SystemVerilog
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
Updated
Mar 31, 2023
SystemVerilog
Updated
Feb 26, 2023
SystemVerilog
ZX Spectrum implementation for maximator board
Updated
Jan 17, 2023
SystemVerilog
UART implementation for my RISCV project
Updated
Jan 10, 2021
SystemVerilog
SPI Interface RTL Description
Updated
May 21, 2019
SystemVerilog
Stress test power subsystem of your Xilinx FPGA board
Updated
Apr 8, 2018
SystemVerilog
Improve this page
Add a description, image, and links to the
soc
topic page so that developers can more easily learn about it.
Curate this topic
Add this topic to your repo
To associate your repository with the
soc
topic, visit your repo's landing page and select "manage topics."
Learn more
You can’t perform that action at this time.