Trying to get a new skill

This project is made using verilog on Xilinx. This will help in changing the pulse width of the output wave by using two signals that are increase duty cycle & decrease duty cycle. This repository contains the verilog module code & also the test bench code.

Design for FPGA of a Universal Asynchronous Receiver Transmitter.

IPcore wrapper for a signed subtractor in VHDL.

A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.

Aid tools for automation of a Xen hypervisor server. Some of the scripts and configurations here are helpful in setting the environment for developmental testing.