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uvm

Here are 3 public repositories matching this topic...

rggen / rggen

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

Updated Jul 20, 2024
Ruby

taichi-ishitani / rggen

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

code-generator rtl verilog csr systemverilog soc uvm ral control-register status-register

Updated Aug 1, 2019
Ruby

rggen / rggen-systemverilog

SystemVerilog RTL and UVM RAL model generators for RgGen

rtl systemverilog uvm ral

Updated Jun 7, 2024
Ruby

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