An FPGA design for simulating biological neurons
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Updated
May 24, 2024 - SystemVerilog
An FPGA design for simulating biological neurons
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
implementation of a basic computer having ability to perform logic and arithmetic operations
This Repository shows the implementation and results of various codes that I write in Verilog HDL
Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u
In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
This is an alarm clock made using Icarus Verilog as part of my Digital Design(DD) project.
During the EL-203 course, we had to make a elevator controller project under Professor Biswajit Mishra.
Traffic light controller for three way intersections
RISC-V single-cycle processor written in Verilog using the Quartus tool. Implementation of bubble sort through assembly language.
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
x and y are input signals representing the x and y coordinates, respectively, each being 1-bit wide.
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
Restoring division for unsigned integer.
NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
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