A small utility to reverse bit order of the output bitstream generated by Quartus ii before it can be flashed into the FPGA flash memory of the arduino vidor MK4000.

Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required