Vitis In-Depth Tutorials

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

Notes on the Eclypse Z7 development board

Ultra96 (v1) projects for Vitis platform

Ultra96 (v1 & v2) projects

CyDAQ DSP Platform Firmware and Software Redesign - Iowa State University Senior Design May 2023 Group 47 - Blake Fisher, Cole Langner, Corbin Kems, Jens Rasmussen, Long Zeng, Wyatt Duberstein, Yohan Bopearatchy

Xilinx Kria KV260 Vision AI Starter Kit

Microblaze demo for Vivado and Vitis 2024.1.

Example workflow project for firmware development in Vitis.

A TFTP server running on Zynq-7000

Fully-automated Vivado + SDK example that tests an emulated JTAG TAP controller

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.

Error detection enabled tau-NAF conversion on Koblitz Curves

Vince's Vitis workspace for RSDecoder. Platform, system, and application for the RSDecoder hardware

Baremetal C application that displays encoder values on a serial interface, starting from a Vivado block design and transitioning to a Vitis application.

Ultra96-V2 Vitis Platform for Xilinx Design Tools version 2020.1

example of using iio to stream data from AD9361 with a coax cable loopback