vitis
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3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
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Apr 13, 2024 - VHDL
In this project I wanted to implement a microprocessor on an FPGA with the ability to write files onto an SD card (micro SD in particular) exploiting the Arty A7 development board and the Digilent PModSD.
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May 3, 2022 - VHDL
Reconfigurable Systems on Chip Mini Project
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Sep 17, 2020 - VHDL
Implementation of a (soft) coprocessor for the computation of a 16 bit LFSR.
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Sep 17, 2021 - VHDL
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