vivado
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3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
MultiCycle and Pipelined Processor designed for the course Computer Organisation of TUC
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Jun 5, 2022 - VHDL
University of Pittsburgh ECE 1195
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Apr 16, 2023 - VHDL
Usese the zybo and nexys 4 ddr to play a game of breakout.
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Aug 13, 2020 - VHDL
Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).
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Apr 2, 2022 - VHDL
Zynq Design Example
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Sep 19, 2022 - VHDL
FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)
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Dec 12, 2023 - VHDL
SE2A4 | Semestre n°8 - Programmation VHDL de FPGA sous Vivado
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May 18, 2021 - VHDL
An 8-bit processor in VHDL based on a simple instruction set
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Mar 7, 2019 - VHDL
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