vivado
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3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).
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Apr 2, 2022 - VHDL
SE2A4 | Semestre n°8 - Programmation VHDL de FPGA sous Vivado
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May 18, 2021 - VHDL
Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.
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Dec 12, 2022 - VHDL
Template for using Xilinx Vivado and SDK with CMPE-661 (HWSW Crypto) projects in a version control friendly way.
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Jun 12, 2023 - VHDL
FPGA-based real-time audio spectrum analyzer.
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Feb 18, 2024 - VHDL
N-bit Multiplier implementation in VHDL
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Jan 22, 2024 - VHDL
This repository contains the VHDL files for a Nanoprocessor Design
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Jun 11, 2023 - VHDL
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Aug 27, 2021 - VHDL
project for DE1 team assignment (D. Caban, I. Dovicak, M. Kováč, L. Kudrna)
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Apr 28, 2022 - VHDL
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