High level synthesis projects and practices
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Updated
Apr 13, 2021 - C++
High level synthesis projects and practices
Custom IP for the Mini-EUSO PDM-DP Zynq system
FPGA Cryptography for High-Level Synthesis
Small project to track things with a waterproof sonar sensor
Hardware accelerator for Image processing in FPGA
This demo is intended to demonstrate the FPGA design protection and metering capability provided by the Accelize Distribution Platform.
Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo
A library of VHDL components for Neural Networks
FPGA and firmware images for the USRP2 to operate as a Wireless Firewall (WiFire)
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
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