FPGA and firmware images for the USRP2 to operate as a Wireless Firewall (WiFire)
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Updated
Jun 22, 2017 - C++
FPGA and firmware images for the USRP2 to operate as a Wireless Firewall (WiFire)
Custom IP for the Mini-EUSO PDM-DP Zynq system
This demo is intended to demonstrate the FPGA design protection and metering capability provided by the Accelize Distribution Platform.
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo
High level synthesis projects and practices
FPGA Cryptography for High-Level Synthesis
A library of VHDL components for Neural Networks
Hardware accelerator for Image processing in FPGA
Small project to track things with a waterproof sonar sensor
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