Detect macaques with Xilinx KV260! Powered by CenterNet
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Updated
Feb 24, 2022 - Python
Detect macaques with Xilinx KV260! Powered by CenterNet
Torii HDL Board Definitions
This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
Eye Cleaner for Xilinx transceivers
Deploying Deep Learning on FPGA: an assessment of ConvNets performance on Xilinx Zynq MPSoC using Vitis-AI development platform
Xilinx Hackathon 2017 Project for tracking the number of cars in an arbitrary number of parking lots with an arbitrary number of entrances.
AI High-Performance Solution on FPGA
The Flow to Deploy your Custom Deep Learning Models on Ultra96V2.
Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit.
Python bindings for Basler's VisualApplets TCL script generation.
Xilinx Picoblaze Assembly Simulator and Debugger
A command line utility to generate bitstreams and various programming files easily for PLDs
AI High-Performance Solution on FPGA
Python wrapper for Xilinx's XSCT/XSDB console
Visual System Integrator - Accelerate your embedded development
A Python-based IP Core Management Infrastructure.
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