SCART Output Reference

SCART Output Reference

The PICO9918 supports SCART RGBs output in both PAL and NTSC timing modes. This page documents the timing specifications and voltage levels for SCART output.

SCART output is enabled at compile time with the -DPICO9918_SCART_RGBS=ON flag. See Building from Source for build instructions.

Auto detection

The SCART dongle is automatically detected at power-on by testing continuity between the HSYNC and VSYNC signals. If the signals are deemed to be connected, the PICO9918 will enter SCART output mode. On the dongle, the two signals are connected via a 1kΩ resistor.

Once the output mode is detected, the auto-detection routine is NOT re-run, so you must power off your device to change output dongles.

Output Modes

Mode	Resolution	Field Rate	Build Flag
NTSC	720x480i	60 Hz (59.94)	-DPICO9918_SCART_RGBS=ON
PAL	720x576i	50 Hz	-DPICO9918_SCART_RGBS=ON -DPICO9918_SCART_PAL=ON

Both modes use interlaced output at 13.5 MHz pixel clock. The PICO9918 uses 1x vertical scaling in SCART mode (no line doubling), unlike VGA mode which uses 2x scaling.

PAL Timing

Frame / Field Timing

Parameter	Value
Total lines per frame	625
Field rate	50 Hz
Field structure	Interlaced (odd/even fields, 312-313 lines each)
Recommended visible lines	~288 (safe across all TVs)
Actual visible lines (typical)	~266, starting ~28 lines below vsync

Non-interlaced mode: Using identical sync pulse train (Field 1 format) for both fields produces 312-line fields at 50.0801 Hz (negligible deviation).

Horizontal Line Timing (64 us total)

|<-- 4us -->|<-- 8us -->|<------------ 52us ------------>|
   HSYNC lo   back porch       picture data
              (color burst
               goes here)

Segment	Duration	Notes
Hsync pulse (low)	4 us	Active low
Back porch	8 us	Required even in RGB mode
Picture data	52 us	Full window
Visible pixel window (typical)	~48.5 us	Starts ~1.25 us into picture data
Hsync frequency	15,625 Hz
Total line period	64 us

Pixel Clock Options

Rate	Notes
14.75 MHz	Standard PAL pixel clock
7.375 MHz	Non-interlaced variant
8 MHz	Simplifies sync calculations

Vertical Sync Pulse Structure

Each field's vsync region consists of three pulse groups: pre-equalizing, long sync, and post-equalizing.

Field 1

[6 pre-equalizing] [5 long sync] [5 post-equalizing]

Field 2

[5 pre-equalizing] [5 long sync] [4 post-equalizing]

Pulse Formats (each group occupies half a line = 32 us)

Pulse Type	Low Duration	High Duration
Equalizing pulse	2 us	30 us
Long sync pulse	30 us	2 us

SCART Voltage Levels

Sync (Pin 20)

Level	Voltage
Sync (active low)	0 V
Black	0.3 V

RGB Channels (Pin 15 = R, Pin 11 = G, Pin 7 = B)

Level	Voltage
Peak (full intensity)	0.7 V
Off (zero intensity)	0.0 V

Important: RGB outputs must be blanked (held low) during sync and back porch periods - the first 12 us of each line.

RGB Mode Enable (Pin 16)

Condition	Value
Activation range	1-3 V
Practical	5V through 100 Ohm gives ~2.1V at TV (75 Ohm load)

Audio (if used)

Parameter	Value
Pin 2	Left / mono
Pin 6	Right
Signal level	1 V peak-to-peak
Impedance	~20 kOhm

Load Impedance

All signal lines present 75 Ohm at the TV end.