Skip to content

Physical Design

Jump to bottom
Richard Huang edited this page Jul 29, 2026 · 2 revisions

Physical Design

The Physical Design team is responsible for transforming the verified RTL into a manufacturable GDSII while meeting performance, power, area (PPA), and signoff requirements.

Objectives

  • Achieve timing closure at the target frequency
  • Minimize area and power
  • Meet all DRC/LVS requirements
  • Produce tapeout-ready GDSII

Flow Overview

RTL
 ↓
Synthesis (Genus)
 ↓
Floorplanning
 ↓
Power Planning
 ↓
Placement
 ↓
Clock Tree Synthesis (CTS)
 ↓
Routing
 ↓
Post-Route Optimization
 ↓
Static Timing Analysis
 ↓
Physical Verification
 ↓
Tapeout (GDSII)

Design Stages

RTL Handoff

  • RTL freeze
  • SDC constraints
  • UPF (if applicable)
  • Library and LEF files

Synthesis

  • Technology mapping
  • Timing optimization
  • Area optimization
  • Power optimization

Deliverables:

  • Netlist
  • Reports
  • Constraints

Floorplanning

  • Core sizing
  • Macro placement
  • IO placement
  • Blockages
  • Pin assignment

Deliverables:

  • Initial DEF
  • Floorplan reports

Power Planning

  • Power rings
  • Power stripes
  • Standard cell rails
  • IR-drop planning

Deliverables:

  • Power grid
  • IR analysis

Placement

  • Global placement
  • Detailed placement
  • Congestion optimization
  • Buffer insertion

Deliverables:

  • Placed DEF
  • Congestion reports

Clock Tree Synthesis

  • Clock buffering
  • Skew optimization
  • Latency balancing
  • Hold fixing

Deliverables:

  • CTS database
  • Clock reports

Routing

  • Global routing
  • Detailed routing
  • Antenna fixes
  • DRC cleanup

Deliverables:

  • Routed DEF
  • DRC reports

Signoff

  • Static Timing Analysis (STA)
  • IR Drop
  • EM Analysis
  • DRC
  • LVS
  • Power analysis

Deliverables:

  • Signoff reports
  • GDSII

Tools

Stage Tool
Synthesis Cadence Genus
Floorplan / P&R Cadence Innovus
Timing Cadence Tempus
Power Cadence Voltus
DRC/LVS Siemens Calibre

Documentation

Clone this wiki locally