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Richard Huang edited this page Aug 3, 2026 · 2 revisions

Signoff

Signoff is the final verification gate before a design is committed to silicon. It answers one question with evidence: is this database manufacturable and functionally correct?

Everything before signoff used implementation-tool models — fast, approximate, tuned for optimization. Signoff re-verifies with independent, foundry-qualified tools using the golden decks. When the two disagree, signoff wins.

Objectives

  • Physical correctness — the layout obeys every foundry design rule
  • Logical correctness — the layout matches the schematic/netlist
  • Timing correctness — all paths pass across all views with extracted parasitics
  • Electrical robustness — IR drop, EM, and signal integrity within budget
  • Reliability — antenna, ESD, latch-up protection
  • Traceability — every check has an archived, reproducible result

Where It Fits

flowchart LR
    A[Routing] --> B[Extraction<br/>Quantus]
    B --> C[STA<br/>Tempus]
    A --> D[DRC / LVS<br/>Pegasus]
    A --> E[Rail analysis<br/>Voltus]
    C --> F[Signoff review]
    D --> F
    E --> F
    F --> G[Tapeout Checklist]
    style F fill:#2d6a9f,color:#fff
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The tools named here are the Cadence signoff set: Pegasus for DRC/LVS, Tempus for STA, Voltus for power integrity, Quantus for extraction. Equivalent checks exist in every vendor's toolchain.

The Signoff Checks

Check Question Tool
DRC Does the layout obey foundry geometry rules? Pegasus
LVS Does the layout match the netlist? Pegasus
ERC Are there electrical rule violations (floating gates, shorted supplies)? Pegasus
Antenna Will charge accumulation damage gate oxide during fab? Pegasus
STA Do all paths meet timing in all views? Tempus
SI Is crosstalk delay/noise within budget? Tempus
IR drop Does every cell see adequate voltage? Voltus
EM Will the metal survive the product lifetime? Voltus
Extraction What are the real parasitics? Quantus
Density / fill Is metal density within CMP limits? Pegasus
LEC Is the final netlist logically equivalent to RTL? Conformal

Physical Verification

DRC — Design Rule Check

Compares layout geometry against the foundry rule deck: minimum width, spacing, enclosure, density, via rules, and (in advanced nodes) multi-patterning colouring constraints.

Why it exists: rules encode what the fab can actually print reliably. Violating them means low yield or non-functional silicon.

Common violations: spacing near macro boundaries, density in sparse regions, antenna on long nets, min-area on small metal stubs.

LVS — Layout Versus Schematic

Extracts a netlist from the layout and compares it to the reference netlist — device by device, connection by connection.

Common failures: power/ground naming mismatches, missing or incorrect macro connections, UPF and implementation disagreeing on power domains, unconnected pins the router silently skipped.

Why LVS failures are dangerous: they mean the chip you fabricate is not the chip you verified. There is no partial credit.

Antenna

During fabrication, a long metal segment connected to a gate but not yet to a diffusion accumulates plasma-induced charge, which can rupture the gate oxide. Fixed with antenna diodes or by jumping to a different layer.

Signoff STA

Signoff timing differs from implementation timing in three ways: independent tool, extracted parasitics (SPEF from Quantus), and full corner coverage with SI enabled.

# Tempus
read_lib -max slow.lib -min fast.lib
read_verilog design.routed.v
read_spef design.spef
read_sdc top.sdc

set_analysis_mode -analysis_type onChipVariation -cppr both
set_si_mode -delta_delay_annotation_mode all

update_timing
report_timing -max_paths 100
report_timing -early -max_paths 100
report_analysis_coverage
report_constraint -all_violators
  • -cppr both — removes double-counted pessimism on the shared clock path
  • set_si_mode — enables crosstalk delta delay, which can shift paths by tens of ps
  • report_analysis_coverage — the check people forget; unconstrained paths are unverified paths

Expect small differences between Innovus and Tempus results. Large differences mean a setup mismatch — chase it rather than accepting whichever number you prefer.

Power Integrity

# Voltus
set_rail_analysis_mode -method dynamic -accuracy high
set_power_data -format vcd activity.vcd
analyze_rail -type domain VDD
report_rail_results

Static analysis uses average current and runs fast. Dynamic analysis uses a real switching trace from Verification and catches the transient hotspots static averages away. Sign off on dynamic.

Electromigration analysis checks current density in every wire and via against foundry limits, factoring in temperature and expected lifetime.

Logical Equivalence Checking

LEC (Cadence Conformal) proves the final gate-level netlist is logically equivalent to the RTL. This matters because implementation tools restructure logic aggressively — cloning, remapping, retiming, scan insertion — and a bug in that transformation would otherwise go undetected.

Common LEC issues: scan chain insertion, clock gating changes, don't-care optimization differences, and retiming. Each needs a documented mapping or waiver.

Metrics

Metric Target
DRC violations 0, or documented foundry-approved waivers
LVS Clean — no discrepancies
Antenna violations 0
Setup / hold WNS ≥ 0 across all views, with SI
Analysis coverage ~100%
Static IR drop ≤ 2–3% VDD
Dynamic IR drop ≤ 5% VDD
EM current density Within foundry limit
Metal density Within min/max per layer
LEC Equivalent, all points mapped

Common Problems

Problem Root cause Fix
Thousands of DRCs in a region Congestion during Routing Fix upstream; local rerouting rarely converges
LVS power mismatch UPF vs. implementation disagreement Re-check domain boundaries, isolation, always-on nets
LVS opens on macro pins Router skipped a pin verify_connectivity; add explicit connections
Tempus and Innovus disagree Different SPEF, libs, or SDC Diff the setups; never just pick the better number
Timing fails only with SI Crosstalk delta delay Shield or space aggressors; upsize victim drivers
Dynamic IR fails, static passed Static averaged away the transient Add decap; densify PDN locally
Density violations in sparse areas Not enough metal Insert fill (do this before final DRC)
LEC non-equivalence Scan insertion or clock gating Set up the correct mapping; investigate every real mismatch

Waivers: some DRC violations are genuinely acceptable and foundry-approved. Every waiver must be documented with a justification and a reviewer name, and archived with the database. An undocumented waiver is a silent bug.

Best Practices

  • Run signoff checks early and often. The first DRC run should not be the week before tape-out. Run on a partially routed database to find systemic problems while they're cheap.
  • Use the golden decks. Foundry-supplied rule decks, foundry-qualified tool versions. Not the implementation tool's approximation.
  • Sign off on extracted parasitics with SI enabled. Anything else is an estimate.
  • Sign off dynamic IR with a real activity trace, sourced from Verification.
  • Archive everything — decks, tool versions, logs, reports, waivers, and the database. Reproducibility matters when something surfaces months later.
  • Never waive something you don't understand. If you can't explain why a violation is safe, it isn't.
  • Freeze the design before signoff. Late ECOs invalidate completed checks and are the classic source of tapeout mistakes.

See also: Timing Closure · Routing · Power Planning · Tapeout Checklist · Physical Design

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