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Richard Huang edited this page Aug 3, 2026 · 2 revisions

Power Planning

Power planning builds the power distribution network (PDN) — the metal that carries VDD and VSS from the pads to every transistor on the die. It happens right after Floorplanning and before Placement, because the grid consumes routing resource that later stages must design around.

Get it wrong and the symptoms appear much later: cells that switch slower than their Liberty models promise, timing that won't close no matter how much you optimize, or metal that fails in the field.

Objectives

  • Deliver voltage — every cell sees close to nominal VDD under worst-case switching
  • Survive current — metal wide enough that electromigration doesn't erode it over the product lifetime
  • Spend metal wisely — every strap is routing resource Routing can't use
  • Support power domains — switchable regions, isolation, level shifters
  • Stay verifiable — the grid must pass rail analysis and LVS

Where It Fits

flowchart LR
    A[Floorplanning] --> B[Power Planning]
    B --> C[Placement]
    C --> D[CTS]
    D --> E[Routing]
    E --> F[Rail analysis<br/>+ signoff]
    F -.->|IR violations| B
    style B fill:#2d6a9f,color:#fff
Loading

The dashed line matters: IR drop isn't truly known until placement and routing are done and real switching activity is available. Early PDN work is an educated guess that gets validated late.

The Core Physics

IR drop. Current through resistance creates a voltage drop: V_drop = I × R. A cell at the far end of a resistive path sees less than nominal VDD, and its delay grows — roughly 1% VDD loss costs a bit more than 1% speed. Budget is typically ≤ 5% of VDD total (static + dynamic).

Electromigration (EM). Sustained current density physically moves metal atoms, eventually opening the wire. Lifetime follows Black's equation — it depends steeply on current density and temperature. This is why wide straps exist even where IR drop alone wouldn't require them.

Why a grid, not a tree. A mesh gives every cell many parallel paths to the supply. Parallel resistance drops fast, and a mesh is robust — one blocked route doesn't starve a region. This is why PDNs are built as regular grids rather than optimized tree structures.

PDN Structure

Element Layer Purpose
Follow-pin rails M1 Horizontal VDD/VSS rails inside each standard cell row
Straps / stripes Mid metal (M4–M6) Vertical and horizontal grid distributing power across the core
Power rings Upper metal Surround the core; collect from pads and feed the straps
Macro rings Varies Local rings around SRAMs and hard IP
Trunks Top thick metal Low-resistance highways from pads to rings
Vias / via stacks All Connect the layers — often the real resistance bottleneck

Rows alternate orientation so adjacent rows share VDD and VSS rails — that's why standard cell rows are flipped.

Why upper metal carries power: top layers are thick, so their sheet resistance is far lower. Lower layers are thin and resistive — fine for local rails, useless for global distribution.

Cadence Innovus Flow

# 1. Connect logical power to physical nets
connect_global_net VDD -type pg_pin -pin_base_name VDD -all
connect_global_net VSS -type pg_pin -pin_base_name VSS -all

# 2. Core ring — collects from the pads
add_rings -nets {VDD VSS} -type core_rings -follow core \
          -layer {top M6 bottom M6 left M5 right M5} \
          -width 5 -spacing 2 -offset 2

# 3. Macro rings — local supply for SRAMs
add_rings -nets {VDD VSS} -type block_rings \
          -around each_block -layer {top M4 bottom M4 left M3 right M3} \
          -width 2 -spacing 1

# 4. The mesh — the main grid
add_stripes -nets {VDD VSS} -layer M5 -direction vertical \
            -width 2 -spacing 2 -set_to_set_distance 40 \
            -start_from left
add_stripes -nets {VDD VSS} -layer M6 -direction horizontal \
            -width 2 -spacing 2 -set_to_set_distance 40

# 5. Standard cell rails
route_special -connect core_pin -nets {VDD VSS}

# 6. Check
verify_power_via
report_power

What the key options mean:

  • -width — strap width. Wider = lower resistance, better EM, but more blocked routing.
  • -set_to_set_distance — grid pitch. Tighter = better IR, less routing left.
  • -direction — straps alternate direction per layer, matching each layer's preferred routing direction.
  • route_special -connect core_pin — drops the M1 follow-pin rails and vias into every row.

Rail analysis

set_pg_library_mode -power_grid_library {tech.cl}
set_rail_analysis_mode -method static
analyze_rail -type domain VDD
report_rail_results

Run static early (average current, quick) and dynamic later with a real activity file (.vcd or .saif) from Verification — dynamic catches the transient hotspots that static misses.

The Central Tradeoff

More metal in the PDN means better IR drop and EM margin — and less routing resource for signals.

Choice Helps Costs
Wider straps IR, EM Blocks more routing tracks
Tighter pitch IR uniformity Blocks more routing tracks
More layers in the grid Lower total resistance Fewer signal layers
Denser via stacks Removes the usual bottleneck Area and DRC pressure

Typical starting point: PDN consumes roughly 20–30% of the tracks on the layers it uses. Tune from rail analysis and congestion results, not from guesswork.

Power Domains

Multi-voltage and power-gated designs add structure. Domains must be contiguous physical regions — decided back in Floorplanning.

Element Role
Power switch (header/footer) Gates supply to a shutdown domain
Isolation cell Clamps outputs of an off domain to a safe value
Level shifter Translates between voltage domains
Always-on buffer Stays powered inside a gated region
Retention flop Preserves state through shutdown

Power intent is captured in UPF (Unified Power Format) and must match the physical implementation exactly — mismatches surface as LVS or connectivity failures at Signoff.

Metrics

Metric Typical target How to improve
Static IR drop ≤ 2–3% of VDD Widen straps, tighten pitch, add vias
Dynamic IR drop ≤ 5% of VDD total Spread high-activity logic; add decap
EM current density Within foundry limit Widen straps and via arrays
PDN routing overhead ~20–30% of tracks used Balance against Routing congestion
Decap ratio ~5–10% of core area Add near high-switching regions

Common Problems

Problem Root cause Fix
IR hotspot under compute array High sustained switching in a small area Locally densify straps; add decap; spread the array
Via-limited resistance Grid looks fine but via stacks are sparse Increase via count/arrays at every crossing
Congestion after PDN Grid too dense for the metal stack Reduce pitch or move straps to a higher layer
Floating power pins Macro pins missed by route_special verify_power_via; add explicit macro connections
LVS power mismatch UPF and implementation disagree Re-check domain boundaries and isolation placement
Passes static, fails dynamic Static averages away the transients Always run dynamic with a real activity file

Decoupling capacitance deserves special mention: decaps are local charge reservoirs that supply instantaneous current so the grid doesn't have to. They're the standard fix for dynamic IR — cheap, and best placed near the switching that causes the problem.

Best Practices

  • Build the PDN before Placement — cells must be placed around the grid, not the reverse
  • Run static rail analysis on the very first grid; don't wait for signoff to discover the topology is wrong
  • Keep the grid regular — uniform pitch is easier to verify, debug, and hand off
  • Check via count, not just strap width; vias are usually the actual bottleneck
  • Reserve the core-to-IO margin at Floorplanning time for the ring
  • Budget PDN track usage explicitly so Routing isn't surprised
  • Get a real activity file from Verification — worst-case guesses are either wildly pessimistic or dangerously wrong

See also: Floorplanning · Placement · Signoff · Physical Design

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