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Design Constraints

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泽宇黄 edited this page Aug 2, 2026 · 1 revision

Design Constraints

Design constraints define the timing, electrical, and operating requirements the implementation flow must honor to produce a correct, performant, and manufacturable design. Constraints are captured in Synopsys Design Constraint (SDC) format and consumed by synthesis, place-and-route, CTS, and signoff STA.

Objectives

  • Define target operating frequencies and clock relationships
  • Specify I/O timing at the block and chip boundary
  • Model realistic operating conditions (PVT, RC corners)
  • Communicate design intent (exceptions, exclusions) to EDA tools
  • Provide a single source of truth reused across synthesis, PnR, and signoff

Constraint Categories

  • Clock definitions — primary clocks, generated clocks, virtual clocks, clock groups
  • Clock uncertainty — jitter, skew, and margin budgets pre- and post-CTS
  • I/O constraints — input_delay / output_delay referenced to boundary clocks
  • Driving cells and loads — set_driving_cell, set_load to model off-chip environment
  • Timing exceptions — false paths, multicycle paths, min/max delay overrides
  • Case analysis — mode configuration for test, scan, and functional views
  • Design rule constraints — set_max_transition, set_max_capacitance, set_max_fanout
  • Operating conditions — PVT corners, derating (OCV/AOCV/POCV)

File Organization

constraints/
 ├── common/
 │    ├── clocks.sdc          # clock creation, groups, uncertainty
 │    ├── io.sdc              # boundary I/O delays and loads
 │    └── exceptions.sdc      # false paths, multicycle paths
 ├── modes/
 │    ├── func.sdc            # functional mode case analysis
 │    ├── scan.sdc            # scan-shift mode
 │    └── atspeed.sdc         # at-speed capture mode
 └── top.sdc                  # sources the above for the target block

Each block owns its own top.sdc; shared collateral lives under common/ and is version-controlled with the RTL.

Flow Usage

RTL + SDC
   ↓
Synthesis (Genus)          ← pre-CTS uncertainty, ideal clocks
   ↓
Floorplan / Placement      ← same SDC, propagated clocks off
   ↓
Clock Tree Synthesis       ← switch to propagated clocks
   ↓
Routing / Post-Route Opt   ← post-CTS uncertainty, real RC
   ↓
Signoff STA (Tempus / PT)  ← multi-mode multi-corner (MMMC)

Authoring Guidelines

  • Create every clock explicitly; never rely on inferred clocks
  • Group asynchronous clocks with set_clock_groups -asynchronous
  • Reference I/O delays to the same clock that launches or captures the signal
  • Prefer set_multicycle_path over set_false_path when a real timing relationship exists
  • Keep exceptions narrow — scope by -from, -to, -through with specific pins
  • Comment every exception with the reason and the reviewing engineer
  • Lint constraints with check_timing and report_exceptions before handoff

Review and Signoff

  • SDC lint (check_timing, report_disable_timing) must be clean before PnR
  • Constraint diffs are reviewed alongside RTL changes
  • MMMC scenarios are locked prior to signoff; any late change requires PD lead approval
  • Final constraints are archived with the tapeout database

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