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Richard Huang edited this page Aug 3, 2026 · 2 revisions

Routing

Routing connects every pin in the design with actual metal. Placement decided where cells sit and Clock Tree Synthesis built the clock network; routing draws the remaining wires and vias on the metal stack, obeying every foundry design rule.

It is the last stage where the design can still be made to work, and the first stage where parasitics are real rather than estimated.

Objectives

  • Complete connectivity — every net routed, zero opens
  • DRC clean — no spacing, width, via, or density violations
  • Timing — critical nets on fast layers, short paths
  • Signal integrity — control crosstalk between neighbouring wires
  • Manufacturability — via redundancy, antenna rules, metal density

Where It Fits

flowchart LR
    A[CTS] --> B[Global Route]
    B --> C[Track Assign]
    C --> D[Detail Route]
    D --> E[Post-route opt]
    E --> F[Extraction<br/>SPEF]
    F --> G[Signoff]
    style B fill:#2d6a9f,color:#fff
    style C fill:#2d6a9f,color:#fff
    style D fill:#2d6a9f,color:#fff
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After routing, parasitic extraction produces SPEF, and Timing Closure finally has real numbers instead of estimates.

The Three Stages

Stage What it does Granularity
Global routing Plans which coarse regions (GCells) each net passes through Region-level, no exact wires
Track assignment Assigns nets to specific routing tracks on each layer Track-level
Detailed routing Draws real geometry and fixes every DRC violation Exact shapes and vias

Global routing is fast and predicts congestion — that's why it's used during Floorplanning and Placement as a feasibility check. Detailed routing is slow and is where DRC violations actually get resolved.

The Metal Stack

Layers alternate preferred direction — horizontal, vertical, horizontal — so that any two points can be reached with few turns.

Layers Character Used for
Lower (M1–M3) Thin, high resistance, fine pitch Local cell-to-cell connections
Middle (M4–M6) Balanced Block-level routing, power straps
Upper (M7+) Thick, low resistance, coarse pitch Long-haul signals, clock, power

Why this matters for timing: a long net stuck on M2 is dramatically slower than the same net promoted to M7. Layer promotion is one of the most effective post-route timing fixes available. In FinFET nodes lower-metal resistance is severe enough that this is often the only fix that works.

Signal Integrity

Adjacent wires couple capacitively. When an aggressor switches, it disturbs its victim:

  • Crosstalk delay — the victim speeds up or slows down depending on switching direction. Can be tens of picoseconds.
  • Crosstalk noise (glitch) — a static victim gets a transient pulse. If large enough, it propagates as a false value.

Fixes, in rough order of preference: increase spacing, insert shielding (grounded wires alongside), upsize the victim driver, promote to a higher layer, or reroute away from the aggressor.

Manufacturing Rules

Rule What it is Fix
Antenna Long metal connected to a gate during fabrication accumulates charge and damages the oxide Insert antenna diodes, or jump to a higher layer
Via redundancy Single vias are a yield risk Convert to double/redundant vias
Metal density Foundry requires min and max density per window for CMP planarity Insert metal fill (usually post-route)
Minimum area Metal shapes below a minimum area are illegal Tool extends the shape

Cadence Innovus Flow

# NanoRoute settings
set_db route_design_detail_post_route_spread_wire true
set_db route_design_with_timing_driven true
set_db route_design_with_si_driven true
set_db route_design_antenna_diode_insertion true

# Route
route_design -global_detail

# Or step through
route_design -global
route_design -track_assign
route_design -detail

# Check
check_drc
report_route -summary
verify_connectivity -type all
verify_drc

# Post-route optimization
extract_rc
opt_design -post_route
opt_design -post_route -hold

# Extract parasitics for signoff
write_spef design.spef

What matters:

  • route_design_with_timing_driven — routes critical nets on better layers and shorter paths
  • route_design_with_si_driven — spaces and shields nets to control crosstalk
  • extract_rc — computes real parasitics; everything before this was an estimate
  • opt_design -post_route — the last chance to fix timing; changes here can create new DRCs, so it's iterative

Non-default rules for critical nets

create_route_rule -name wide_rule -width_multiplier 2 -spacing_multiplier 2
set_db net:critical_bus route_rule wide_rule

Shielding

route_special -shield_net VSS -nets {clk_main} -shield_side both_side

Metrics

Metric Target If it's bad
DRC violations Zero Reduce congestion; more routing effort; check Floorplanning
Opens / shorts Zero verify_connectivity; usually a congestion symptom
Routed wirelength Minimize Correlates with power and delay
Via count Minimize Vias add resistance; excess means excessive layer changes
Post-route WNS/TNS Meet target Layer promotion, NDR, resize drivers
SI-induced delta delay Small More spacing, shielding, stronger drivers
Antenna violations Zero Diode insertion, layer jumping

The jump from pre-route to post-route timing is often unpleasant — estimated parasitics are optimistic. Expect it and leave margin.

Common Problems

Problem Root cause Fix
Thousands of DRCs in one region Local congestion Fix upstream: density target, blockages, macro placement
Routing never converges Design fundamentally over-utilized Reduce utilization; this is a Floorplanning problem
Timing much worse post-route Real parasitics vs. estimates Promote critical nets to upper layers; NDR; resize
Crosstalk failures Long parallel runs on the same layer Shield, space, or reroute
Antenna violations Long metal on one layer to a gate input Diodes or layer jumping
Post-route opt creates new DRCs Cell resizing disturbs routed geometry Iterate opt and route incrementally
Clock nets degraded Routed like ordinary signals Apply NDR and shielding to clock — see Clock Tree Synthesis

Best Practices

  • Congestion is decided upstream. If detail routing fails, the fix is almost always in Floorplanning or Placement, not in routing options.
  • Check global route congestion before committing to a long detail route run. Detail routing a hopeless design wastes hours.
  • Reserve upper layers for what needs them — clock, long buses, power. Don't let routine nets consume the fast layers.
  • Apply NDRs selectively. Wide-and-spaced routing on everything just creates congestion.
  • Expect post-route timing to be worse than post-CTS. Budget for it.
  • Run verify_connectivity and verify_drc before declaring done — the router's own report isn't signoff.
  • Keep DRC counts trending down run over run. A count that plateaus means a structural problem.

Longhorn Silicon Notes

  • MatE's array boundary is the routing hotspot. PE-to-PE connections inside the array are short and local — nearly free. The operand broadcast entering the array and the result drain leaving it are wide, high-activity, and timing-critical. Reserve upper-layer resource for them and consider NDRs on the broadcast buses.
  • KV cache buses are wide and fast. The KVE↔MatE data path is high bandwidth by design. These are prime candidates for layer promotion and, if crosstalk shows up, for shielding.
  • SRAM macros block lower layers. Routing over KVE banks must use whatever layers the macro abstract leaves free. Check the abstract early — this constrains how much over-macro routing is available and can force detours you didn't plan for.
  • Watch crosstalk on the broadcast networks. Long parallel wide buses switching at high activity every cycle is exactly the aggressor pattern SI analysis flags.
  • Clock and high-activity data compete for the same good layers. Decide the layer budget deliberately rather than letting the router arbitrate.

Student tapeout notes

  • GF180MCU (SSCS Chipathon) — this is the big one. A thin metal stack means routing resource is genuinely scarce, and the PDN (Power Planning) is competing for it. Congestion will appear at utilizations that would be comfortable in a modern node. Plan for 60–70% and treat routability as the binding constraint on array size.
  • Sky130 — more layers than GF180, good for practising the flow.
  • N16FFC — double patterning on lower layers adds colouring constraints, and lower-metal resistance makes layer promotion essential rather than optional.
  • OpenROAD equivalent — grt (global, FastRoute) and drt (detailed, TritonRoute). ROUTING_CORES, GRT_ADJUSTMENT, and the DRT variables in OpenLane control the equivalent behaviour. TritonRoute is genuinely readable if you want to understand what a detail router does.
  • Practical advice — route one PE, look at the actual geometry in the GUI, and find the DRC violations by hand once. It makes every later log message legible.

References

  • Cadence Innovus User Guide, NanoRoute chapters — authoritative for the commands above
  • Kahng, Lienig, Markov, Hu — VLSI Physical Design — global and detailed routing algorithms (maze routing, channel routing, Steiner trees)
  • Cadence Quantus documentation — parasitic extraction and what SPEF actually contains
  • OpenROAD grt / drt (TritonRoute) docs — open-source routers with published papers
  • Foundry design rule manuals — the actual rules; nothing substitutes for reading your PDK's DRM

See also: Placement · Clock Tree Synthesis · Timing Closure · Signoff · Physical Design

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