May has been a monumental month for the PLCT Lab. Last month, three of our members presented at the EuroLLVM 2023 conference in Glasgow, Scottland. This has been PLCT's first trip abroad. Another item of note is that we have officially announced "RUYISDK," our official WeChat outlet. In the future, you will find coverage on our products, developer profiles, and more.
In June, we will hold our first RuyiSDK Open Day 如意开放日, where we will share development progression on our SDK components. Event schedules and registration information will be available on the "RUYISDK" page.
- Chinese: The ISCAS Upstreamed LIBCXX-SIMD
- Chinese: openEuler RISC-V Receives First Prize at the Chinese Open Source Innovation Competition
- Chinese: ISCAS 2023 Open Day
Backported upstream patches:
- 4553932: [riscv][masm] Improve Instance Type Checks in Builtins::Call/Construct | https://chromium-review.googlesource.com/c/v8/v8/+/4553932
- 4541408: [riscv] Unify pointer size | https://chromium-review.googlesource.com/c/v8/v8/+/4541408
- 4543857: [riscv][static-roots]Port static-root | https://chromium-review.googlesource.com/c/v8/v8/+/4543857
- 4525059: [riscv] Implement probe mmu mode | https://chromium-review.googlesource.com/c/v8/v8/+/4525059
- 4541402: [riscv] Support acq/rel accesses and atomic accesses on tagged | https://chromium-review.googlesource.com/c/v8/v8/+/4541402
- 4521076: [riscv]Enable caged heap | https://chromium-review.googlesource.com/c/v8/v8/+/4521076
- 4505078: [riscv][builtins] Remake Api callback thunk wrappers calling convention | https://chromium-review.googlesource.com/c/v8/v8/+/4505078
- Reviewed jdk-mainline pull requests.
- openjdk/jdk#11996 (JDK-8299229: [JVMCI] add support for UseZGC)
- openjdk/jdk#13794 (8303153: Native interpreter frame missing mirror)
- openjdk/jdk#13771 (8307058: Implementation of Generational ZGC)
- openjdk/jdk#13983 (8308091: Remove unused iRegIHeapbase() matching operand)
- openjdk/jdk#13577 (8306667: RISC-V: Fix storeImmN0 matching rule by using zr register)
- openjdk/jdk#13645 (8291550: RISC-V: jdk uses misaligned memory access when AvoidUnalignedAccess enabled)
- openjdk/jdk#13684 (8306966: RISC-V: Support vector cast node for Vector API)
- openjdk/jdk#13739 (8307150: RISC-V: Remove remaining StoreLoad barrier with UseCondCardMark for Serial/Parallel GC)
- openjdk/jdk#13800 (8307446: RISC-V: Improve performance of floating point to integer conversion)
- openjdk/jdk#13862 (8307609: RISC-V: Added support for Extract, Compress, Expand and other nodes for Vector API)
- openjdk/jdk#13881 (8307651: RISC-V: stringL_indexof_char instruction has wrong format string)
- openjdk/jdk#13882 (8307758: RISC-V: Improve bit test code introduced by JDK-8291555)
- openjdk/jdk#14029 (8308277: RISC-V: Improve vectorization of Match.sqrt() on float)
- openjdk/jdk#14102 (8308656: RISC-V: vstring_compare doesnt manifest usage of all vector registers)
- Reviewed/Merged backported patches for the
riscv-port-jdk17u
repo.- openjdk/riscv-port-jdk17u#45 (8293566: RISC-V: Clean up push and pop registers)
- openjdk/riscv-port-jdk17u#46 (8294012: RISC-V: get/put_native_u8 missing the case when address&7 is 6)
- openjdk/riscv-port-jdk17u#47 (8294679: RISC-V: Misc crash dump improvements)
- openjdk/riscv-port-jdk17u#48 (8296435: RISC-V: Small refactoring for increment/decrement)
- openjdk/riscv-port-jdk17u#49 (8297359: RISC-V: improve performance of floating Max Min intrinsics)
- openjdk/riscv-port-jdk17u#50 (8296916: RISC-V: Move some small macro-assembler functions to header file)
- openjdk/riscv-port-jdk17u#51 (8306667: RISC-V: Fix storeImmN0 matching rule by using zr register)
- openjdk/riscv-port-jdk17u#52 (8308089: [riscv-port-jdk17u] Intrinsify Unsafe.storeStoreFence)
- openjdk/riscv-port-jdk17u#53 (8297697: RISC-V: Add support for SATP mode detection)
- openjdk/riscv-port-jdk17u#54 (8301036: RISC-V: Factor out functions baseOffset & baseOffset32 from MacroAssembler)
- openjdk/riscv-port-jdk17u#55 (8307150: RISC-V: Remove remaining StoreLoad barrier with UseCondCardMark for Serial/Parallel GC)
- Submitted and merged JDK-mainline patches.
- openjdk/jdk#13862 | (8307609: RISC-V: Added support for Extract, Compress, Expand and other nodes for Vector API)(as co-authur)
- openjdk/jdk#14138 | (8308817: RISC-V: Support VectorTest node for Vector API )(as co-authur)
- openjdk/jdk#14166 | (8308915: RISC-V: Improve temporary vector register usage avoiding the use of v0)
- openjdk/jdk#14197 | (8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit)(as co-authur)
- Backport jdk17u:
- openjdk/riscv-port-jdk17u#50 | (8296916: RISC-V: Move some small macro-assembler functions to header file)
- openjdk/riscv-port-jdk17u#54 | (8301036: RISC-V: Factor out functions baseOffset & baseOffset32 from MacroAssembler)
- openjdk/riscv-port-jdk17u#59 | (8301628: RISC-V: c2 fix pipeline class for several instructions)
- openjdk/riscv-port-jdk17u#60 | (8301852: RISC-V: Optimize class atomic when order is memory_order_relaxed)
- Upstreamed patches.
- openjdk/jdk#13862 | (8307609: RISC-V: Added support for Extract, Compress, Expand and other nodes for Vector API)(as co-author)
- openjdk/jdk#14138 | (8308817: RISC-V: Support VectorTest node for Vector API )(as co-author)
- openjdk/jdk#14197 | (8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit)(as co-author)
- Backported patches for the
riscv-port-jdk17u
repo.- openjdk/riscv-port-jdk17u#53 | (8297697: RISC-V: Add support for SATP mode detection)
- openjdk/riscv-port-jdk17u#61 | (8301153: RISC-V: pipeline class for several instructions is not set correctly)
- openjdk/riscv-port-jdk17u#64 | (8302289: RISC-V: Use bgez instruction in arraycopy_simple_check when possible)
No update this month.
- Upstreamed patches.
- [ValutTracking] Use isGuaranteedNotToBePoison in impliesPoison https://reviews.llvm.org/D149934
- [InstSimplify] Simplify select i1 ConstExpr, i1 true, i1 false to ConstExpr https://reviews.llvm.org/D151631
- [RISCV] Support '.option arch' directive https://reviews.llvm.org/D123515
- [LVI] Don't compute range on not guaranteed not to be undef condition in SelectInst https://reviews.llvm.org/D151295
- [ValueTracking][InstCombine] Add a new API to allow to ignore poison generating flags or metadatas when implying poison https://reviews.llvm.org/D149404
- [LoopIdiom] Freeze BitPos if !isGuaranteedNotToBeUndefOrPoison https://reviews.llvm.org/D151690
- zfinx codegen https://reviews.llvm.org/D148874
- zdinx rv64 codegen https://reviews.llvm.org/D149665
- zdinx rv32 codegen https://reviews.llvm.org/D149743
- [RISCV][CodeGen] Support Zhinx and Zhinxmin https://reviews.llvm.org/D149811
- Zcmt MC https://reviews.llvm.org/D133863
- Zcmp MC https://reviews.llvm.org/D132819
- [RISCV] Enable signed truncation check transforms for i8 https://reviews.llvm.org/D150177
- [RISCV] Fold (select setcc, setcc, setcc) into and/or instructions https://reviews.llvm.org/D150286
- [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v https://reviews.llvm.org/D151176
- [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT https://reviews.llvm.org/D151719
You may find more of our code review by searching under the names of the authors above.
All patches were updated or revised, awaiting next round of review.
- Submitted support enhancements for RV64-ILP32, upstream review underway.
- https://sourceware.org/pipermail/binutils/2023-May/127501.html
- Slide deck://docs.google.com/presentation/d/1JbA5Zkq1F__wuaF5RYWK9XDlC-Lf9ZJLP-0jRF74a6A/edit#slide=id.p
- Discussed
lw
/sw
usage in RV64-ILP psABI's e_flags. - Optmizing RVV test generator, referencing SPIKE. https://github.com/XYenChi/intrinsic-testcase-generator/tree/optimize-version
- Discussed optimizations for Zcmp implementation with ESWIN. Performance benchmark and rebase pending.
- Submitted Profiles specifications to riscv-toolchain-covensions.
- Jeff joined work to impelemnt BF16 support in the GNU toolchain. riscv-admin/dev-partners#30
- RISC-V GNU Toolchain Bi-Weekly Meeting slide decks:
[core] 257 / 264 (97.34%) [extra] 12185 / 13244 (92.00%)
- Arch Linux RISC-V 中文社区 on Telegram: https://t.me/+zTnGwO5zNKAyNmU1
- IRC: #archlinuxriscv at libera.chat
- Matrix: #archlinux-riscv:matrix.org
- Finished merging
community
intoextra
- Enabled several kernel configs to support All Winner D1
- Lichee Pi 4a image and rootfs link 1
- Note that this file's designed usage is to replace the inner rootfs provided by this image: link 2
fastboot flash ram uboot.bin
fastboot reboot
fastboot flash uboot uboot.bin
fastboot flash boot boot.ext4
fastboot flash root rootfs.ext4 # <-- only this file is from the first link
- glibc: [PATCH v3] riscv: Add macros for FPUCW/fcsr in fpu_control.h link
- gcc: [RFC PATCH] driver: unfilter default library path [PR 104707] link
- qemu: linux-user: Add some ioctls for mesa amdgpu support link
- tutorial for running graphic softwares inside qemu-user with AMD Radeom Graphic Card: link
- gnu-efi: CHAR8 needs to be defined; BOOLEAN does not need to be defined here link
- box64: riscv64 support (4 PRs by xctan @ Arch Linux RISC-V) (Please refer to #Box64 section)
- rust: Bump
cc
forbootstrap
link - libopenshot:
- napi-rs:
- lychee: test(client): make exponential_backoff better link
- alt-pytest-asyncio: test: fix flaky test on slow machines link
- jumpy: build: upgrade mimalloc to 0.1.36. link
- JuPyMake: Split compiler flags by whitespace. link
- pyalpm: test: fix test_db_{grpcache_pkg_segfault,read_grp} link
- syscalls:
- nix: Add implementation of
PTRACE_{GET,SET}REGSET
link - plz: Add riscv64 support link
Stats: 7810/18757, 41.64% (https://whale.plctlab.org/riscv/support-statistics/)
- A total of 22 keywording commits (include non-PLCT team members): https://whale.plctlab.org/riscv/stats/2023_05.txt
- dev-ruby/asciidoctor: re-keyword 2.0.20 riscv
- media-libs/mesa: re-keyword 23.1.0 riscv
- media-sound/rhythmbox: Keyword 3.4.7-r1 riscv
- net-libs/libiscsi: re-keyword 1.19.0_p20230208 riscv
- A new wiki page for how to install Gentoo Linux on the board with T-Head TH1520 RISC-V SoC
- 4 u-boot commits which enable the basic support of TH1520
- t-head: licheepi4a: initial support, dlan17/u-boot@bca3adc
- dts: t-head: basic device tree for Sipeed Lichee PI 4A board, dlan17/u-boot@db820a7
- configs: th1520_lpi4a_defconfig: basic config for Sipeed Lichee PI 4A, dlan17/u-boot@478eef5
- doc: thead: lpi4a: document Lichee PI 4A board, dlan17/u-boot@bd9e71a
- Start thinking about big-endian support
- tracker bug: https://bugs.gentoo.org/907135
- original request: https://bugs.gentoo.org/907029
- gnu-efi: patch to fix build for riscv64 NixOS/nixpkgs#234128
- udp2raw: build with cmake NixOS/nixpkgs#231599
- tests.pkg-config.defaultPkgConfigPackages NixOS/nixpkgs#231600
- stubby: fix sourceRoot for cross compilation NixOS/nixpkgs#231601
- mesa-demos: fix cross compilation, set strictDeps NixOS/nixpkgs#231603
- mawk: fix cross compilation NixOS/nixpkgs#231604
- ftxui: set strictDeps, fix cross compilation NixOS/nixpkgs#233409
- xfsprogs: fix cross compilation NixOS/nixpkgs#233765
- x265: fix cross compilation to non-aarch64 NixOS/nixpkgs#233470
- treewide: move pkg-config to nativeBuildInputs NixOS/nixpkgs#234899
- xplorer: move cmake to nativeBuildInputs NixOS/nixpkgs#234898
- starfive visionfive2: update kernel to 6.4.0-rc3 NixOS/nixos-hardware#630
- apfs-snap: do not hardcode CC linux-apfs/apfsprogs#10
- https://phabricator.services.mozilla.com/D177449
- https://phabricator.services.mozilla.com/D178616
- https://bugzilla.mozilla.org/show_bug.cgi?id=1831496
This month, we worked predominantly on RV64-related infrastructures, but programs still do not run. We aim to see Hello World running on DynamoRIO in the coming month.
Merged pull requests:
- ksco
- shiptux
- i#3544 riscv64: Fixed CALLC for RISC-V and Implemented some instructions
- i#3544 riscv64: Implemented dr_setjmp and dr_longjmp
- i#3544 riscv64: Implemented dynamorio_condvar_wake_and_jmp
- i#3544 riscv64: Implement some base instructions
- i#3544 RV64: Implemented dynamorio-clone
- i#3544 riscv64: Implemented atomic_swap and Improved atomic_add
- i#6027: define w8 only for AArch64
Pending pull requests:
- ksco
- i#3544 RV64: Added an encoder and some fixes and improvments to the decoder
- i#3544 RV64: Small improvments to some assembly functions
- i#3544 RV64: Implement TLS functions
- i#3544 RV64: Fixed dynamorio_syscall
- i#3544 RV64: Fixed atomic functions and macros
- i#3544 RV64: Added machine type support for ELF hdr verification
[WIP] Automated OpenCV Universal Intrinsic code migrator for the RVV backend.
- Detects Universal Intrinsic types.
- Supports rewriting vector lengths and overloaded operators in vector types.
- Git repository: https://github.com/hanliutong/rewriter
- Upstream work.
- Merged patches.
- Accepted patches.
- Patches under review.
- D144698:[libcxx] <experimental/simd> Removed original implementations and tests
- D144363:[libcxx] <experimental/simd> Added aliagned flag types, some simd traits and related tests
- D144364:[libcxx] <experimental/simd> Added internal storage type, constructors, subscript operators of class simd/simd_mask and related tests
- Other work-in-progress items.
- Refactored tests for the
where
operator and improved test coverage. - Added AArch64 tests in GitHub Action CI - https://github.com/fepicture/llvm-project/actions/workflows/simd_aarch64_nightlytest.yml.
- Test RISC-V compilation, the SIMD library successfully generated RVV instructions.
- Refactored tests for the
- We announced an OSPP 2023 project, Chinese: 基于C++标准库experimental/simd的OpenCV后端移植与优化.
This month, we focused our work on JIT tracing. We tuned the trace number handling scheme and revamped the exit number handler. Additionally, the interpreter has received some adjustments and the IR assembler has picked up many fixes.
-
Interpreter
-
JIT
- Added the
vcompress
instruction. - Added the
vle8ff.v
,vle16ff.v
,vle32ff.v
, andvle64ff.v
instructions. - Fixed a bug in the
makeWriter
function.
At the time of writing, we have implemented all RISC-V vector instructions, with the exception of segment load/restore. You may find our work-in-progress code at the plct-gem5 repository's rvv-cpu branch for testing and feedback.
Updated BF16 support to v0.6.0, riscv-software-src/riscv-isa-sim#1321
- Submitted patches.
- Update Zc* extensions, https://lists.gnu.org/archive/html/qemu-riscv/2023-05/msg00266.html
- Fixes for PMP issues (v6), https://lists.gnu.org/archive/html/qemu-riscv/2023-05/msg00336.html
- Add support for disassembling extensions with encoding conflicts (v2), https://lists.gnu.org/archive/html/qemu-riscv/2023-05/msg00441.html
- Add support for PC-relative translation (v3), https://lists.gnu.org/archive/html/qemu-riscv/2023-05/msg00540.html
- Fixes for pointer mask (v7), https://lists.gnu.org/archive/html/qemu-riscv/2023-05/msg00476.html
- Fixes for mstatus, https://lists.gnu.org/archive/html/qemu-riscv/2023-05/msg00573.html
- Add support for Zacas, https://github.com/plctlab/plct-qemu/tree/plct-zacas-dev
- Update support for BF16 extensions, https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream-v2
- Add support for PM v0.5.4, https://github.com/plctlab/plct-qemu/tree/plct-pm-0.5.4
This month, we continued to improve the dynamic recompiler for the RV64 JIT backend and continued work on abstraction libraries. We care pleased to report that the RV64 backend is now usable! As we get closer to a new release, the box64 author also wrote a report on the forthcoming RISC-V support.
Upstreamed pull requests.
- xctan
- ksco
- Added some wayland function wrappers
- Added more opcodes
- Fixed 66 0F CMOV opcodes
- Fixed 66 0F 38 2B PACKUSDW opcode
- Added 4 more libc dprintf wrappers
- Added vwprintf (for #793)
- Fixed stack align on varargs (for #789)
- Added 1 more symbol for libc (for #787)
- Added some missing fixes on GETEX
- Use the new x9 scratch register
- Forget mmx float reg only needed
- Added more 0F MMX opcodes and some fixes
- Added more opcodes and some fixes
- Remove redundant code
- Added 1 libx11 symbol for #758
- Added more opcodes and some fixes
- Added more opcodes and a small fix
- Used RunFunctionFmt for better sign-extend handling
- Fixed typos in (67) 88 MOV opcode
- Added more opcodes
- Added some mpg123 wrapped functions
- Added some AES opcodes
- Added more opcode for Unciv and some fixes
- Added more opcodes for Unciv
- Added more opcodes for Bastion and some fixes
- Updated CMO extension support in SAIL, riscv/sail-riscv#137
Shi Ninging (史宁宁) continues to work on compiling the OpenArkCompiler Weekly, which just published its 163th issue.
You may find new weekly issues of the OpenArkCompiler Weekly on Sundays on...
- GitHub: https://github.com/isrc-cas/arkcompiler-materials
- Zhihu: https://zhuanlan.zhihu.com/openarkcompiler
- Bilibili: https://www.bilibili.com/read/readlist/rl199373
- Mailing list and other channels: https://gitee.com/openarkcompiler/OpenArkCompiler/issues/I1EWAX
EuroLLVM 2023 (https://llvm.swoogo.com/2023eurollvm)
- Buddy Compiler: An MLIR-based Compilation Framework for Deep Learning Co-design (Speaker: Hongbin Zhang)
- RISC-V Vector Extension Support in MLIR: Motivation, Abstraction, and Application (Speaker: Hongbin Zhang)
- Buddy-CAAS: Compiler As A Service for MLIR (Speaker: Hongbin Zhang)
- Image Processing Ops as first class citizens in MLIR: write once, vectorise everywhere! (Speaker: Prathamesh Tagore)
Proposed a unified RRV and ARM SVE vectorization design with the following observations:
- ARM SVE does not need variable vector length support as per RVV.
- ARM SVE does not need to support vsetvl-based strip-mining vectorization as per RVV.
- ARM SVE does not support VP Intrinsic.
- Based on our evaluation of AXPY and a convolutional vectorization, we found that strip-mining vectorization has a slight performance advantage over mask-based methods. We plan to run more benchmarks for further analysis.
- References:
- Sparsity: https://blog.sh1mar.in/post/sparsity/intro/
- Sparse Tensor Implmentation in Sparse Compiler and MLIR: https://blog.sh1mar.in/post/sparsity/compiler/
- Buddy Compiler Homepage - https://buddy-compiler.github.io/
- Buddy Compiler's OSPP 2023 Project Home - https://summer-ospp.ac.cn/org/orgdetail/8d995d4c-b188-4690-9a53-c022dc7c19e3?lang=zh
buddy-caas
Buddy Compiler As A Service(Buddy-CAAS)- https://buddy.isrc.ac.cn/
- Supports x86 and RISC-V backends, as well as quick code verification and testing across multiple backends.
- Added support for more use cases, each with default Pass Pipeline and configuration support.
buddy-mlir
Code repository: https://github.com/buddy-compiler/buddy-mlir
- Added buddy-lsp-server.
- Added support for Fast Fourier Transform.
- Added an one-step building method.
buddy-benchmark
Code repository: https://github.com/buddy-compiler/buddy-benchmark
- Added the linpackc vectorization benchmark.
- Completed preliminary design for RISC-V Vector long vector RTL and commenced review in reference to Buddy Compiler use cases.
- Submitted revision suggestions for Land and LSU bottlenecks, began work on refactoring Lane.
- Commenced work on Chisel-CIRCT bind using MLIR C-API and jextract.
No update this month.
No update this month.
- lib: sbi: Optimize probe of srst/susp
- lib: sbi: Fix return of sbi_console_init
- lib: utils: Improve fdt_serial_init
- Improve
fdt_ipi
andfdt_timer
, remove dummy driver, and prepone initialization loop. 1 2 - lib: sbi: Ensure SBI extension is available
- Makefile: Dereference symlinks on install
- platform: generic: add T-HEAD th1520 soc support
- lib: reset: thead: Remove unnecessary fence operations
- lib: reset: thead: Correct the naming convention of dts
- lib: utils/ipi: buffer overrun aclint_mswi_cold_init
No update this month.
- v0.30 Correctly count usage in recursive definitions PR-983 opened by AliasQli
- v0.30 Fix baka let and add some improvement PR-982 opened by HoshinoTented
- v0.30 Fix native-image build PR-980 opened by imkiva
- v0.30 Parse only selected languages in markdown PR-981 opened by imkiva
- v0.30 KALA: upgrade to 0.67.0 PR-977 opened by Glavo
- v0.30 Fix some bad code PR-976 opened by HoshinoTented
- v0.29 Release 0.29 PR-975 opened by ice1000
- v0.29 Fix #972.5 PR-974 opened by HoshinoTented
- v0.29 Fix #972 PR-973 opened by HoshinoTented
- v0.29 KALA: upgrade to 0.66.0 PR-971 opened by Glavo
- 0.19 Upgrade & Fix Compile PR-30 opened by HoshinoTented
- eunomia-bpf
- #222: Support multiple export types
- Added support and examples for xdp: #223: add xdp support, #243: add xdp example
- Published
ecli
andecc
on crates.io: #231, #238 - #232: fix ecli ctrlc
- #236: [ecc] Support producing standalone executables
- CI-related fixes: #234, #235, #249
- #247: Adapt ecli and bpf-loader with bpf-compatible-rs
- #252: Add profile support
- Developed a new project, bpf-compatible, to fix dependency libraries with eBPF version incompatibilities, per request from openEuler.
- wasm-bpf
- bpf-developer-tutorial
This month, we improved our SPEC CPU automation scripts, which is now able to download and build specific GCC/LLVM versions, run SPEC CPU2017 tests, and output benchmark results. Moreover, for SPEC CPU tuning, we began to survey impact of all compiler flags used by SPEC2017 to help improve results. Do achieve this, we used a script to collect all compiler flags used and rank them by the frequency on which they were used.
- SPEC CPU automation script.
https://github.com/mollybuild/RISCV-Measurement/tree/master/scripts/Run-SPEC-CPU
- SPEC CPU2017 compiler flags survey.
Collection and sorting results, https://github.com/mollybuild/RISCV-Measurement/tree/master/scripts/getflags
The following image shows compiler flags used by SPEC CPU2017, sorted by frequency:
- Kernel CI deployment.
- Implemented Unmatch and VisionFive jobs under LAVA.
- Adapted kernelci-docker code and deployed Kernel CI frontend and backend databases.
- Implemented interoperation between LAVA jobs and kernelci.
- Implemented an automation script in Python to create lab and lab tokens using Kernel CI's backend API, https://github.com/jiewu-plct/kernel-ci/blob/main/creat-lab.py
- Fixed an issue where logs could not be reviewed on the kernelci interface.
- Fixed implicit token access via kernelci backend with LAVA jobs.
- LTP syscalls use case now runs via LAVA on Unmatched.
- Assembled documentation on deploying and using LAVA and Kernel CI, https://github.com/jiewu-plct/kernel-ci
- Automation scripts.
- Script to fetch package revisions changes in specific projects and build results from specific repository/architecture combos, https://github.com/isrc-cas/tarsier-oerv/tree/main/scripts/obs_pkgstatus
- PLCT's 2022 Roadmap, https://github.com/plctlab/PLCT-Weekly/blob/master/PLCT-Roadmap-2022.md
- Job openings at the PLCT Lab, https://github.com/plctlab/PLCT-Weekly/blob/master/Jobs.md
- Intern openings at the PLCT Lab, https://github.com/plctlab/weloveinterns/blob/master/open-internships.md
- PLCT Weekly Reports, https://github.com/isrc-cas/PLCT-Weekly
- PLCT Open Reports (Selected), https://github.com/isrc-cas/PLCT-Open-Reports