All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog and this project adheres to Semantic Versioning.
No changes.
v0.7.0 2021-06-18
- Make
Clocks
ppre1()
andppre2()
methods public, to get the current Prescaler value. (#210) - Support for more CAN bit rates and modes. (#186)
- Implement
into_xxx
methods for partially erased pins (#189) - Enable better GPIO internal resistor configuration (#189)
- Support for GPIO output slew rate configuration (#189)
- Support for GPIO interrupts (#189)
ld
feature, which enables the memory.x generation (#216)- Implement
DelayMs
forMilliseconds
andDelayUs
forMicroseconds
(#234) - ADC can now be
free()
'd (#212) - Serial does now implement
embedded_hal::serial::{Read, Write}
. Nosplit()
necessary. (#232) - Serial can now listen for the "Transmission Complete"
Tc
interrupt event (#232) - Serial can now listen for the
Idle
interrupt event (#238)
- The structure of
gpio.rs
is greatly changed. GenericPin
struct is used for every GPIO pin now (#189)
- Delay based on systick no longer panics (#203) for to high values and support longer delays (#208)
- Long delay during ADC initialization (#217)
- The MSRV was bumped to 1.51 (#227)
- Replace custom time based units with types defined in the embedded-time crate (#192)
- The
rcc
public API now expects time based units inMegahertz
. If the supplied frequency cannot be converted toHertz
the code willpanic
. This will occur if the suppliedMegahertz
frequency cannot fit intou32::MAX
when converting toHertz
(#192)
// The supplied frequencies must be in `MHz`.
let clocks = rcc
.cfgr
.use_hse(8.MHz())
.hclk(48.MHz())
.sysclk(48.MHz())
.pclk1(12.MHz())
.pclk2(12.MHz())
- You always required to select a sub-target for target chips (#216)
- Bump dependencies: (#229)
cortex-m
to 0.7.2cortex-m-rt
to 0.6.4defmt
to 0.2.2embedded-hal
to 0.2.5nb
to 1.0.0stm32f3
to 0.13.2stm32-usbd
to 0.6.0
into_afx
methods are splitted intointo_afx_push_pull
andinto_afx_open_drain
(#189)- GPIO output mode (
PushPull
orOpenDrain
) is encoded into pin typestate in alternate function mode (#189) - GPIO internal resistor configuration is no longer encoded into pin typestate in input mode (#189)
- Remove
stm32
module. Useuse stm32f3xx_hal::pac
instead. This module was a deprecated in v0.5.0 and is now subject for removal. (#220) Serial::uart1
... functions are renamed toSerial::new
. (#212)
v0.6.1 - 2020-12-10
- Removed
doc-comment
dependency (#184)
v0.6.0 - 2020-12-10
- Support for 16-bit words with SPI (#107)
- SPI support for reclock after initialization (#98)
- Support for
stm32f302x6
andstm32f302x8
devices (#132) - Support for the onboard real-time clock (RTC) (#136)
- Enable DMA for USART on
stm32f302
devices (#139) - Basic CAN bus support (#100)
- Impls for all SPI pins for all
stm32f302
sub-targets,stm32f303
subtargets,stm32f3x8
targets,stm32f334
, andstm32f373
(#99) - SPI4 peripheral for supported devices. (#99)
- Support for I2C transfer of more than 255 bytes, and 0 byte write (#154)
- Support for HSE bypass and CSS (#156)
- Impls for missing I2C pin definitions (#164)
- Support I2C3 (#164)
- Support for
defmt
(#172)- Now defmt features are available.
- Currently these are only used for panicking calls, like
assert!
panic!
orunwrap()
. These are enabled using the defmt filter. - For now defmt is mostly intended for internal development and testing to further reduce panicking calls in this crate. The support of this feature is subject to change as the development of defmt is advancing.
- Introduced auto-generated GPIO mappings based on the STM32CubeMX database (#129)
- Fixed #151 not being able to generate 72 MHz HCLK for stm32f303xc devices (#152)
- Wrong I2C clock source (#164)
- Removed impl for
SckPin<SPI2>
forPB13<AF5>
fromstm32f328
andstm32f378
targets. (#99) - Removed SPI1 support for
stm32f302x6
andstm32f302x8
sub-targets andstm32f318
target. (#99) - This release requires 1.48, as intra-doc-links are now used internally. Until now, no MSRV was tracked. This has changed now. This however does not mean, that we guarantee any MSRV policy. It is rather for documentation purposes and if a new useful feature arises, we will increase the MSRV. (#170)
- Removed I2C2 support for
stm32f303x6
,stm32f303x8
andstm32f328
targets. (#164) I2c::i2c1
andI2c::i2c2
functions are renamed toI2c::new
. (#164)
v0.5.0 - 2020-07-21
- Implement
InputPin
forOutput<OpenDrain>
pins (#114) - Support for safe one-shot DMA transfers (#86)
- DMA support for serial reception and transmission (#86)
- ADC support for
stm32f303
devices (#47)
PLL
was calculated wrong for devices, which do not divideHSI
(#67)
- The system clock calculation is more fine grained now. (#67) Now the system clock can be some value, like 14 MHz, which can not a be represented as a multiple of the oscillator clock:
let clocks = rcc
.cfgr
.use_hse(8.mhz())
.sysclk(14.mhz())
// or
let clocks = rcc
.cfgr
.use_hse(32.mhz())
.sysclk(72.mhz())
This is possible through utilizing the divider, which can divide the external oscillator clock on most devices. Some devices have even the possibility to divide the internal oscillator clock.
- The feature gate requires you to select a subvariant if possible. (#75)
- Split up
stm32f302
into sub-targetsstm32f302xb
,stm32f302xc
,stm32f302xd
,stm32f302xe
- Bump
stm32f3
dependency to0.11.0
(#97) - The
stm32f3
reexport is now renamed fromstm32
topac
(#101) - The correct
stm32f3
modules are now used for thestm32f318
andstm32f738
targets. As a result, some previously (wrongly) supported peripherals have been removed from these targets. (#116)
v0.4.3 - 2020-04-11
- Independent Watchdog (#58)
- Wrong default modes for debug GPIO pins (#82)
- Wrong calculation of HCLK prescaler, if using a prescaler value equal or higher than 64 (#42)
- UART reception error flags not cleared (#91)
v0.4.2 - 2020-03-21
- Bump
stm32f3
dependency to0.10.0
(#70)
v0.4.1 - 2020-03-07
- Use Infallible error type for UART (#50)
- Implement blocking Write for UART (#50)
- Implement blocking Read for I2C (#52)
- Regression in v0.4.0 that set SPI to LSB-first ordering (#60)
v0.4.0 - 2019-12-27
- USB Driver for all devices except
stm32f301
andstm32f334
as they have no USB peripheral. (#24) StatefulOutputPin
andToggleableOutputPin
(#25)- Support devices with 2-bit PLLSRC fields (#31)
- This allows using 72 MHz
sysclk
on thestm32f303
- This allows using 72 MHz
- Analog gpio trait (#33)
- Add PWM Channels (#34)
- SPI embedded hal modes are now public (#35)
- Alternate gpio functions are now only made available for devices, which have them. (#21)
stm32f303
is now split intostm32f303xd
andstm32f303xe
as they provide different alternate gpio functions.stm32f303
is still available.- Bump
stm32f3
dependency to0.9.0
(#39)
- Fixed wrong initialization of the SPI (#35)
v0.3.0 - 2019-08-26
- HSE and USB clock are now supported (#18)
- Bump
stm32f3
version to0.8.0
(#19)
v0.2.3 - 2019-07-07
- Fix timer initialization (#17)
v0.2.2 - 2019-07-06
- Missing
stm32f303
timers (#16)
v0.2.1 - 2019-07-06
- Fully erased pin (#14)
v0.2.0 - 2019-07-02
- Various peripheral mappings for some devices (#12)
- Switch to the
embedded-hal
v2 digital pin trait.
v0.1.5 - 2019-06-11
- Support for GPIO AF14 (#6)
v0.1.4 - 2019-05-04
- Fixed I2C address (#4)
v0.1.3 - 2019-04-12
- Implement GPIO
InputPin
traits (#2)
v0.1.2 - 2019-04-06
- Support
stm32f328
,stm32f358
andstm32f398
devices - Support
stm32f334
device - Support
stm32f378
device - Support
stm32f373
device
v0.1.1 - 2019-03-31
- Support
stm32f301
andstm32f318
devices - Support
stm32f302
device
- Support
stm32f303
device