asic
Here are 93 public repositories matching this topic...
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
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Jun 20, 2024 - Verilog
Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)
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Jun 12, 2024 - Verilog
TT07 resub of tt04-raybox-zero "3D" VGA ray caster demo (like Wolf3D)
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May 31, 2024 - Verilog
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
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May 28, 2024 - Verilog
Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7
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May 25, 2024 - Verilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Apr 30, 2024 - Verilog
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
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Apr 29, 2024 - Verilog
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
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Apr 25, 2024 - Verilog
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
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Apr 19, 2024 - Verilog
Full Speed USB DFU interface for FPGA and ASIC designs
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Mar 10, 2024 - Verilog
Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
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Mar 10, 2024 - Verilog
IC implementation of Systolic Array for TPU
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Mar 4, 2024 - Verilog
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
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Feb 27, 2024 - Verilog
Custom chips reverse-engineered from silicon
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Feb 12, 2024 - Verilog
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