Simulate a statement through Moore FSM, With a full explanation. This project was my last additional course project for Verilog in Digital Systems Design during my BS in Computer Engineering
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Aug 23, 2021 - Verilog
Simulate a statement through Moore FSM, With a full explanation. This project was my last additional course project for Verilog in Digital Systems Design during my BS in Computer Engineering
My Verilog Codes for Digital Systems Design Course
This repository contains projects developed by students of the Bachelor of Computer Engineering program at Qazvin Islamic Azad University (QIAU). The projects cover various topics in computer engineering, including digital systems, microprocessor, logical circuits, computer graphics, and etc..
Digital Systems Design, Sharif University of Technology Fall 2022, Instructor: Dr. Amin Foshati
👾 My studies with Verilog and notions of digital systems.
Implementation of a low-pass FIR filter in Verilog HDL.
My interests and some collaborations
Repository focused on giving a complete introductory course to digital systems, applied to robotics and automation.
DSDS (Digital system design and synthesis) Lab and class programs of 2021 - 25 batch.
Cache Controller Project for COE758 Digital Systems Engineering.
Digital Systems Design Lab, Sharif University of Technology Fall 2022
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
Seven instructions digital processor for general purpose.
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