Simple calculator implemented in VHDL using FSM logic

These are VHDL codes for 12Bit counter to 7segment output. contains binary to BCD converter base on double dabble algorithm.

DoubDabC is a Java library that supports binary integer value to decimal sequence conversion with alternative algorithm.

Implementation of the Double Dabble Algorithm in Verilog to convert a 8 bit binary number to its 3 digit BCD equivalent

golang big number.

Early draft of ARM64 Textbook