DRAM Request Manager for Multicore Processors

Background Test for SWP-Tree

Test DRAM for bit flips caused by the rowhammer problem

MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution

A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput

A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.

MIPS ISA simulator which implements non-blocking DRAM access

Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi

DRAM Tester Shield for Arduino Nano

A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips

HAShCache + Intergrated CPU/GPU system simulation setup

HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/210…

DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.

BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.

Sample Arduino program to test 4164 DRAM chips.

A High-Level DRAM Timing, Power and Area Exploration Tool

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

DRAMSim2: A cycle accurate DRAM simulator

**No Longer Maintained** Official RAMCloud repo