OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Updated
May 6, 2024 - Verilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
A High-performance Timing Analysis Tool for VLSI Systems
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
IceChips is a library of all common discrete logic devices in Verilog
Tools for working with circuits as graphs in python
Plugins for Yosys developed as part of the F4PGA project.
A Standalone Structural Verilog Parser
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
DATC RDF
7 track standard cells for GF180MCU provided by GlobalFoundries.
9 track standard cells for GF180MCU provided by GlobalFoundries.
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
"High density" digital standard cells for SKY130 provided by SkyWater.
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