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RISC V PROCESSOR DESIGN IN VERILOG
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Mar 21, 2024 - Verilog
EDA及其应用大作业,2016,武汉大学 Homework for EDA and its applications, Wuhan University, 2016 Summer
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Feb 20, 2019 - Verilog
Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.
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Oct 30, 2023 - Verilog
Running OpenROAD cloud flow on AES design
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Aug 7, 2019 - Verilog
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Jul 28, 2023 - Verilog
"High speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High voltage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Low power" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
generic NetList data structure for VLSI
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Sep 3, 2023 - Verilog
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
单周期、多周期CPU(Verilog/武汉大学计算机学院计组实验)
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Apr 11, 2017 - Verilog
"Low speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
IEEE DATC Robust Design Flow 2021.
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Jan 8, 2022 - Verilog
This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…
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Mar 30, 2022 - Verilog
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