ES-203 Computer Organization & Architecture CNN on FPGA board
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Updated
Feb 23, 2022 - Verilog
ES-203 Computer Organization & Architecture CNN on FPGA board
Verilog Implementation of Run Length Encoding for RGB Image Compression
My experiments with Nexys4 DDR Artix-7 FPGA Board
🍒 Accelerating CNNs for Facial Expression Recognition [Published in Research in Intelligent and Computing in Engineering 2020]
RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga
UART - RTL Design and Verification
In this project, we implemented a different kind of a tic tac toe board game that is played on an FPGA board using its push buttons. We used Verilog HDL to code the project and implemented a VGA interface for visualization.
This project is part of the B.Tech degree in Electronics and Telecommunication Engineering at KIIT University.
Application of the RANSAC algorithm in embedded C and Verilog for Altera Nios II and Cyclone IV E.
Verilog code for my paper that proposes a secure-AES algorithm with support for various FPGA boards.
These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA
First FPGA Project done on FPGA DE10-Standard. Simple blinking of LED.
simple project using zybo z7 20 which goal is to design fully functioning doorlock
Designing a simple processor system on FPGA. This is demo project to test FPGA DE10-Standard and develop a simpe Nios2 app.
Low Cost FPGA Quadrature Oscillator
A collection of educational and practical Verilog modules for FPGA design, tested on Delite FPGA MAX 10 with Intel Quartus and ModelSim. Includes utilities like Clock Dividers, Debouncers, Decoders, State Machines, and more.
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