gtkwave
Here are 27 public repositories matching this topic...
Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
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Dec 22, 2023 - Verilog
Pre and Post Synthesis Simulation of a Design VSDMemSOC
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May 5, 2024 - Verilog
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
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Dec 6, 2020 - Verilog
This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.
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Jun 16, 2018 - Verilog
Practice Codes of Verilog Language
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Apr 1, 2024 - Verilog
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
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May 8, 2024 - Verilog
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
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Mar 22, 2024 - Verilog
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
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Apr 11, 2024 - Verilog
A completely functional encryption decryption model with specially generated Asymmetric key verification
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Jan 30, 2018 - Verilog
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